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| 型號(hào)： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 90/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
90
12/15/97 5:47 PM 24333502.doc
A.1.42
SLP# (I)
The SLP# (Sleep) signal, when asserted in Stop
Grant state, causes processors to enter the Sleep
state. During Sleep state, the processor stops
providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or
interrupts. The processor will recognize only
assertions of the SLP#, STPCLK#, and RESET#
signals while in Sleep state. If SLP# is deasserted,
the processor exits Sleep state and returns to Stop
Grant state, restarting its internal clock signals to the
bus and APIC processor core units.
A.1.43
SMI# (I)
The SMI# (System Management Interrupt) signal is
asserted asynchronously by system logic. On
accepting
a
System
processors save the current state and enter System
Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins
program execution from the SMM handler.
Management
Interrupt,
A.1.44
STPCLK# (I)
The STPCLK# (Stop Clock) signal, when asserted,
causes processors to enter a low power Stop Grant
state. The processor issues a Stop
Acknowledge transaction, and stops providing
internal clock signals to all processor core units
except the bus and APIC units. The processor
continues to snoop bus transactions and service
interrupts while in Stop Grant state. When STPCLK#
is deasserted, the processor restarts its internal
clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
Grant
A.1.454
TCK (I)
The TCK (Test Clock) signal provides the clock input
for the Pentium II processor Test Bus (also known as
the Test Access Port).
A.1.46
TDI (I)
The TDI (Test Data In) signal transfers serial test
data into the Pentium II processor. TDI provides the
serial input needed for JTAG support.
A.1.47
TDO (O)
The TDO (Test Data Out) signal transfers serial test
data out of the Pentium II processor. TDO provides
the serial output needed for JTAG support.
A.1.48
TESTHI (I)
The TESTHI signal must be connected to a 2.5 V
power source through a 1 –10 k
resistor for proper
processor operation.
A.1.49
THERMTRIP# (O)
The processor protects itself from catastrophic
overheating by use of an internal thermal sensor.
This sensor is set well above the normal operating
temperature to ensure that there are no false trips.
The processor will stop all execution when the
junction temperature exceeds approximately 130 °C.
This is signaled to the system by the THERMTRIP#
(Thermal Trip) pin. Once activated, the signal
remains latched, and the processor stopped, until
RESET# goes active. There is no hysteresis built into
the thermal sensor itself; as long as the die
temperature drops below the trip level, a RESET#
pulse will reset the processor and execution will
continue. If the temperature has not dropped below
the trip level, the processor will continue to drive
THERMTRIP# and remain stopped.
A.1.50
TMS (I)
The TMS (Test Mode Select) signal is a JTAG
support signal used by debug tools.
A.1.51
TRDY# (I)
The TRDY# (Target Ready) signal is asserted by the
target to indicate that it is ready to receive a write or
implicit write back data transfer. TRDY# must
connect the appropriate pins of all Pentium II
processor System Bus agents.
A.1.52
TRST# (I)
The TRST# (Test Reset) signal resets the Test
Access Port (TAP) logic. TRST# must be driven low
during power on reset. This can be accomplished
with a 680
pull-down resistor.
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