PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
6
Table 10. System Bus AC Specifications
(Clock) .................................................27
Table 11. Valid Slot 1 System Bus, Core
Frequency and Cache Bus
Frequencies.........................................28
Table 12. GTL+ Signal Groups System Bus AC
Specifications.......................................28
Table 13. System Bus AC Specifications (CMOS
Signal Group).......................................29
Table 14. System Bus AC Specifications (Reset
Conditions)...........................................29
Table 15. System Bus AC Specifications (APIC
Clock and APIC I/O)............................30
Table 16. System Bus AC Specifications (TAP
Connection)..........................................31
Table 17. BCLK Signal Quality Specifications....37
Table 18. GTL+ Signal Groups Ringback
Tolerance.............................................38
Table 19. Signal Ringback Specifications for Non-
GTL+ Signals.......................................41
Table 20. Pentium II Processor Thermal Design
Specification.........................................43
Table 21. Example Thermal Solution
Performance for 266 MHz Pentium II
Processor at Thermal Plate Power of
37.0 Watts............................................43
Table 22. S.E.C. Cartridge Materials ..................51
Table 23. S.E.C. Cartridge Dimensions..............51
Table 24. Description Table for Processor
Markings ..............................................59
Table 25. Signal Listing in Order by Pin
Number ................................................63
Table 26. Signal Listing in Order by Signal
Name....................................................68
Table 27. Boxed Processor Fan/Heatsink Spatial
Dimensions..........................................75
Table 28. Boxed Processor Fan/Heatsink
Support Dimensions.............................76
Table 29. Fan/Heatsink Power and Signal
Specifications.......................................80
Table 30. BR0# (I/O) and BR1# Signals Rotating
Interconnect.........................................85
Table 31. BR[1:0]# Signal Agent IDs ..................85
Table 32. Slot 1 Occupation Truth Table ............89
Table 33. Output Signals.....................................91
Table 34. Input Signals........................................92
Table 35. Input/Output Signals (Single Driver)....93
Table 36. Input/Output Signals (Multiple Driver).93