- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369993 > pentium II processor (Intel Corp.) 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 85/94頁 |
| 文件大小： | 892K |
| 代理商： | PENTIUM II PROCESSOR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁當(dāng)前第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
85
all Pentium II processor System Bus agents.
Observing BPRI# active (as asserted by the priority
agent) causes all other agents to stop issuing new
requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting
BPRI#.
A.1.13
BR0# (I/O), BR1# (I)
The BR0# and BR1# (Bus Request) pins drive the
BREQ[1:0]# signals in the system. The BREQ[1:0]#
signals are interconnected in a rotating manner to
individual processor pins. Table 30 gives the rotating
interconnect between the processor and bus signals.
Table 30. BR0# (I/O) and BR1# Signals
Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
During power-up configuration, the central agent
must assert the BR0# bus signal. All symmetric
agents sample their BR[1:0]# pins on active-to-
inactive transition of RESET#. The pin on which the
agent samples an active level determines its agent
ID. All agents then configure their pins to match the
appropriate bus signal protocol, as shown in
Table 31.
Table 31. BR[1:0]# Signal Agent IDs
Pin Sampled Active in RESET#
Agent ID
BR0#
0
BR1#
1
A.1.14
BSEL# (I/O)
The BSEL# (Bus Select) signal is used for future
Slot 1 processors and motherboards. This signal
must be tied to GND for proper processor operation.
A.1.15
D[63:0]# (I/O)
The D[63:0]# (Data) signals are the data signals.
These signals provide a 64-bit data path between the
Pentium II processor System Bus agents, and must
connect the appropriate pins on all such agents. The
data driver asserts DRDY# to indicate a valid data
transfer.
A.1.16
DBSY# (I/O)
The DBSY# (Data Bus Busy) signal is asserted by
the agent responsible for driving data on the
Pentium II processor System Bus to indicate that the
data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the
appropriate pins on all Pentium II processor System
Bus agents.
A.1.17
DEFER# (I)
The DEFER# signal is asserted by an agent to
indicate that a transaction cannot be guaranteed in-
order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or I/O
agent. This signal must connect the appropriate pins
of all Pentium II processor System Bus agents.
A.1.18
DEP[7:0]# (I/O)
The DEP[7:0]# (Data Bus ECC Protection) signals
provide optional ECC protection for the data bus.
They are driven by the agent responsible for driving
D[63:0]#, and must connect the appropriate pins of
all Pentium II processor System Bus agents which
use them. The DEP[7:0]# signals are enabled or
disabled for ECC protection during power on
configuration.
A.1.19
DRDY# (I/O)
The DRDY# (Data Ready) signal is asserted by the
data driver on each data transfer, indicating valid
data on the data bus. In a multi-cycle data transfer,
DRDY# may be deasserted to insert idle clocks. This
signal must connect the appropriate pins of all
Pentium II processor System Bus agents.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。