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| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 88/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
88
A.1.31
PICD[1:0] (I/O)
The PICD[1:0] (APIC Data) signals are used for bi-
directional serial message passing on the APIC bus,
and must connect the appropriate pins of all
processors and core logic or I/O APIC components
on the APIC bus.
A.1.32
PM[1:0]# (O)
The PM[1:0]# (Performance Monitor) signals are
outputs from the processor which indicate the status
of programmable counters used for monitoring
processor performance.
A.1.33
PRDY# (O)
The PRDY (Probe Ready) signal is a processor
output used by debug tools to determine processor
debug readiness. See the Pentium
II Processor
Developer’s Manual(Order Number 243341) for
more information on this signal.
A.1.34
PREQ# (I)
The PREQ# (Probe Request) signal is used by
debug tools to request debug operation of the
processors.
See
the
Developer’s Manual(Order Number 243341) for
more information on this signal.
Pentium
II
Processor
A.1.35
PWRGOOD (I)
The PWRGOOD (Power Good) signal is a 2.5 V
tolerant processor input. The processor requires this
signal to be a clean indication that the clocks and
power supplies (Vcc
CORE
, etc.) are stable and within
their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current),
without glitches, from the time that the power
supplies are turned on until they come within
specification. The signal must then transition
monotonically to a high (2.5 V) state. Figure 50
illustrates the relationship of PWRGOOD to other
system signals. PWRGOOD can be driven inactive
at any time, but clocks and power must again be
stable before a subsequent rising edge of
PWRGOOD. It must also meet the minimum pulse
width specification in Table 13 and be followed by a
1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the
processor as it is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD
signal does not need to be synchronized for FRC
operation. It should be driven high throughout
boundary scan operation.
A.1.36
REQ[4:0]# (I/O)
The REQ[4:0]# (Request Command) signals must
connect the appropriate pins of all Pentium II
processor System Bus agents. They are asserted by
the current bus owner over two clock cycles to define
the currently active transaction type.
A.1.37
RESET# (I)
Asserting the RESET# signal resets all processors to
known states and invalidates their L1 and L2 caches
without writing back any of their contents. RESET#
must remain active for one microsecond for a “warm”
reset; for a power-on reset, RESET# must stay
active for at least one millisecond after Vcc
CORE
and
CLK have reached their proper specifications. On
observing active RESET#, all Pentium II processor
System Bus agents will deassert their outputs within
two clocks.
A number of bus signals are sampled at the active-
to-inactive transition of RESET# for power-on
configuration. These configuration options are
described in the Pentium
II Processor Developer’s
Manual(Order Number 243341).
The processor may have its outputs tristated via
power-on configuration. Otherwise, if INIT# is
sampled active during the active-to-inactive transition
of RESET#, the processor will execute its Built-In
Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the
reset-vector (default 0_FFFF_FFF0h). RESET# must
connect the appropriate pins of all Pentium II
processor System Bus agents.
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