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| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 24/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
24
NOTES:
1.
2.
3.
4.
5.
Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
Icc
CORE
and Vcc
CORE
supply the processor core and the L2 cache I/O buffers.
Vcc
L2
and Icc
L2
supply the L2 cache core.
V
TT
must be held to 1.5 V ±9%. It is recommended that V
TT
be held to 1.5 V±3% during System Bus idle.
These are the tolerance requirements, across a 20 MHz bandwidth,
at the Slot 1 connector pins on the bottom side of
the baseboard
. The requirements at the Slot 1 connector pins account for voltage drops (and impedance discontinuities)
across the connector, substrate edge fingers and to the processor core. The Slot 1 connector has the following
requirements: Pin Self Inductance: 10.5 nH(max); Pin to Pin Capacitance: 2pF (max, at 1 MHz); Contact Resistance: 12
m
(max averaged over power/ground contacts). Contact Intel for testing conditions of these requirements.
These are the tolerance requirements, across a 20 MHz bandwidth,
at the processor substrate edge fingers
. The
requirements at the processor substrate edge fingers account for voltage drops (and impedance discontinuities) at the
substrate edge fingers and to the processor core.
The typical Icc
measurements are an average current draw during the execution of Winstone* 96 on a Windows* 95
operating system. These numbers are meant as a guideline only, not a guaranteed specification. Actual measurements will
vary based upon system environmental conditions and configuration.
Max I
CC
measurements are measured at V
CC
nominal voltage under maximum signal loading conditions.
The current specified is the current required for a single Pentium
II processor. A similar current is needed for the opposite
end of the GTL+ bus.
10. The current specified is also for AutoHALT Power Down state.
11. Maximum values are specified by design/characterization at nominal Vcc
CORE
and nominal Vcc
L2
.
12. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance
tolerable and reaction time of the voltage regulator. This parameter is not tested.
13. dI
CC
/dt is measured at the Slot 1 connector pins.
14. Vcc
5
and Icc
5
are not used by the Pentium II processor. This supply is used for debug purposes only.
15. Use Typical Voltage Specification with tolerance level specification to provide correct voltage regulation to the processor.
16. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at
maximum current output, is no greater than the nominal voltage level of Vcc
(Vcc
). In this case, the
maximum current level for the regulator, Icc
CORE_REG
, can be reduced from the specified maximum current Icc
CORE_MAX
and is calculated by the equation:
Icc
CORE_REG
= Icc
CORE_MAX
x Vcc
CORE_TYP
/ Vcc
CORE_MAX
17. This specification applies to CPU ID 63x.
18. This specification applies to CPU ID 65x.
6.
7.
8.
9.
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