參數(shù)資料
型號(hào)： pentium III processor
廠商： Intel Corp.
英文描述： 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 18/67頁(yè)
文件大小： 834K
代理商： PENTIUM III PROCESSOR
Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep
Technology
12
Datasheet
243356-005
3.1.6
Processor and PIIX4E/M Sideband Signals
Table 6
provides descriptions of the processor and PIIX4E/M sideband signals.
NOTE:
See
Table 9
for V_CPUPU definition.
Table 6. Processor and PIIX4E/M Sideband Signal Descriptions
Name
Type
Voltage
Description
FERR#
O D
CMOS
V_CPUPU
Numeric Coprocessor Error:
This pin functions as an FERR# signal
supporting coprocessor errors. This signal is tied to the coprocessor
error signal on the processor and is pulled active low by the processor
to the PIIX4E/M.
IGNNE#
I D
CMOS
V_CPUPU
Ignore Error:
This open-drain signal is connected to the Ignore Error
pin on the processor and is driven by the PIIX4E/M.
INIT#
I D
CMOS
V_CPUPU
Initialization:
INIT# is asserted by the PIIX4E/M to the processor for
system initialization. This signal is an open-drain.
INTR
I D
CMOS
V_CPUPU
Processor Interrupt:
INTR is driven by the PIIX4E/M to signal the
processor that an interrupt request is pending and needs to be serviced.
This signal is an open-drain.
NMI
I D
CMOS
V_CPUPU
Non-Maskable Interrupt:
NMI is used to force a non-maskable
interrupt to the processor.
The PIIX4E/M ISA bridge generates an NMI
when either SERR# or IOCHK# is asserted, depending on how the NMI
Status and Control Register is programmed. This signal is an open-
drain.
A20M#
I D
CMOS
V_CPUPU
Address Bit 20 Mask:
When enabled, this open-drain signal causes
the processor to emulate the address wraparound at 1 MB, which
occurs on the Intel 8086 processor.
SMI#
I D
CMOS
V_CPUPU
System Management Interrupt:
SMI# is an active-low synchronous
output from the PIIX4E/M that is asserted in response to one of many
enabled hardware or software events.
The SMI# open-drain signal can
be an asynchronous input to the processor.
However, in this chipset
SMI# is synchronous to PCLK.
STPCLK#
I D
CMOS
V_CPUPU
Stop Clock:
STPCLK# is an active-low, synchronous open-drain output
from the PIIX4E/M that is asserted in response to one of many
hardware or software events.
STPCLK# connects directly to the
processor and is synchronous to PCICLK.
When the processor samples
STPCLK# asserted, the processor responds by entering a low-power
state (Quick Start). The processor will only exit this mode when this
signal is deasserted.
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