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參數(shù)資料
| 型號： | pentium III processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| 中文描述： | 32位處理器的移動模塊（32位帶移動模塊處理器） |
| 文件頁數(shù)： | 43/67頁 |
| 文件大?。?/td> | 834K |
| 代理商： | PENTIUM III PROCESSOR |
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Pentium
III Processor Mobile Module MMC-2
Featuring Intel
SpeedStep
Technology
243356-005
Datasheet
37
Figure 7. Power Sequence Timing
5.3.3
Power Planes: Bulk Capacitance Requirements
The placement of sufficient bulk capacitance on the system electronics board is critical to the
operation of the mobile module and to ensure that the system design can accommodate future high
frequency modules. Intel has provided the maximum possible bulk capacitance on the mobile
module. However, in order to achieve proper filtering and in-rush current protection, it is
imperative that additional filtering be provided on the system electronics board.
Table 27
details
the bulk capacitance requirements for the system electronics.
Note:
Observe the voltage rating requirement for the capacitors on each respective voltage rail.
NOTES:
1. PW ROK on I/O board should be active on when VR_PW RGD is active and V_3S is good.
2. CPU_RST from I/O board should be active for a minimum of 6.0 mS after PW ROK is active and PLL_STP# and CPU_STP# are inactive.
Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4E/M.
3. This is the 5.0-V power supplied to the MMC-2 connector. This should be the first 5.0-V plane to power up. Stays on during suspend.
4. G_LO/HI# must be high at the rising edge of VR_ON. If it is not, the BIOS must assert this signal very early in core execution.
5. V_DC >= 7.5V, V_5>= 4.5V, V_3S>= 3.0V.
6. VR_PW RGD is specified active by the module regulator within less than or equal to 6.0-mS maximum after the assertion of VR_ON.
7. V_CPUPU and V_CLK are generated on the mobile module.
V_CPUPU
V_CLK
NOTE 7
NOTE 7
VR_PW RGD
V_DC
V_3
V_5
V_3S
VR_ON
G_LO/HI#
NOTE 5
0 MS MIN
NOTE 3
0 MS MIN
NOTE 4
NOTE 6
0 MS MIN
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