參數資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數： | 11/70頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標準包裝： | 90 |
| 應用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 19 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
5.2.4.
Mode Selection
All of the internal UART channels in the I/O Bridge support the 16C450, 16C550, Enhanced 16C550, and
Enhanced 950 UART Modes. The mode of the UART operation is selected by toggling the Special Function
Register (SFR[5]) and Enhanced Function Register (EFR[4]). The FIFO depth of each mode and the mode
selection is tabulated in the table below.
Table 5-1 Mode Selection
UART Mode
SFR[5]
EFR[4]
FIFO Size
450/550
X
0
1/16
Enhanced 550
0
1
128
Enhanced 950
1
128
5.2.5.
450/550 Mode
The 450 Mode is inherently supported when 550 Mode is selected. When in the 450 Mode, the FIFOs are in
the “Byte Mode”, which refers to the one-byte buffer in the Transmit Holding Register and the Receive
Holding Register in each of the UART channels. When in the 550 Mode, the UARTs support an increased
FIFO depth of 16.
When EFR[4] is set to “0”, the SFR[5] is ignored, and the 450/550 Mode is selected.
5.2.6.
Enhanced 550 Mode
Setting the SFR[5] to “0” and EFR[4] to “1” enables the Enhanced 550 Mode. The Enhanced 550 Mode
further increases FIFO depth to 128.
5.2.7.
Enhanced 950 Mode
128-deep FIFOs are supported in the Enhanced 950 Mode. When the Enhanced 950 Mode is enabled, the
UART channels support additional features:
Sleep mode
Special character detection
Automatic in-band flow control
Automatic flow control using selectable arbitrary thresholds
Readable status for automatic in-band and out-of-band flow control
Flexible clock prescaler
Programmable sample clock
DSR/DTR automatic flow control
5.2.8.
Transmit and Receive FIFOs
Each channel of the UARTs consists of 128 bytes of transmit FIFOs and 128 bytes of receive FIFOs,
namely the Transmit Holding Registers (THR) and the Receive Holding Registers (RHR). The FIFOs
provide storage space for the data before they can be transmitted or processed. The THR and RHR operate
simultaneously to transmit and read data.
The transmitter reads data from the THR into the Transmit Shift Register (TSR) and removes the data from
top of the THR. It then converts the data into serial format with start and stop bits and parity bits if required.
If the transmitter completes transmitting the data in the TSR and the THR is empty, the transmitter is in the
idle state. The data that arrive most recently are written to the bottom of the THR. If the THR is full, and
the user attempts to write data to the THR, a data overrun occurs and the data is lost.
13-0093
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