PI7C9X7954
PCI Express Quad UART
Datasheet
Page 43 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.64. ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h
BIT
FUNCTION
TYPE
DESCRIPTION
4:0
First Error Pointer
ROS
It indicates the bit position of the first error reported in the
Uncorrectable Error Status register.
Reset to 00000b.
5
ECRC Generation
Capable
RO
When set, it indicates the I/O bridge has the capability to generate
ECRC.
Reset to 1b.
6
ECRC Generation
Enable
RWS
When set, it enables the generation of ECRC when needed.
Reset to 0b.
7
ECRC Check
Capable
RO
When set, it indicates the I/O bridge has the capability to check
ECRC.
Reset to 1b.
8
ECRC Check
Enable
RWS
When set, the function of checking ECRC is enabled.
Reset to 0b.
31:9
Reserved
RO
Reset to 000000h.
6.2.65. HEADER LOG REGISTER – OFFSET From 11Ch to 128h
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
1st DWORD
RO
Hold the 1st DWORD of TLP Header. The Head byte is in big
endian.
7:4
2nd DWORD
RO
Hold the 2nd DWORD of TLP Header. The Head byte is in big
endian.
11:8
3rd DWORD
RO
Hold the 3rd DWORD of TLP Header. The Head byte is in big
endian.
15:12
4th DWORD
RO
Hold the 4th DWORD of TLP Header. The Head byte is in big
endian.
13-0093