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參數(shù)資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 22/70頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 29 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.14. CAPABILITIES POINTER REGISTER – OFFSET 34h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Capabilities Pointer
RO
This optional register points to a linked list of new capabilities
implemented by the device. This default value may be changed by
auto-loading from EEPROM.
The default value is 80h.
6.2.15. INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Interrupt Line
RW
Used to communicate interrupt line routing information. POST
software will write the routing information into this register as it
initializes and configures the system.
Reset to 00h.
6.2.16. INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Interrupt Pin
RO
Identifies the legacy interrupt Message(s) the device uses.
Reset to 01h.
6.2.17. POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 01h to indicate that these are power management enhanced
capability registers.
6.2.18. NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
The pointer points to the Power Management capability register
(8Ch).
Reset to 8Ch.
6.2.19. POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Power Management
Revision
RO
Read as 011b to indicate the I/O bridge is compliant to Revision 1.1
of PCI Power Management Interface Specifications.
19
PME# Clock
RO
Does not apply to PCI Express. Must be hardwired to 0b.
20
Auxiliary Power
RO
Read as 1b to indicate the I/O bridge forwards the PME# message in
D3cold and an auxiliary power source is required.
21
Device Specific
Initialization
RO
Read as 0b to indicate the I/O bridge does not have device specific
initialization requirements. The default value may be changed by
auto-loading from EEPROM.
24:22
AUX Current
RO
Reset as 111b to indicate the I/O bridge need 375 mA in D3 state.
The default value may be changed by auto-loading from EEPROM.
25
D1 Power State
Support
RO
Read as 1b to indicate the I/O bridge supports the D1 power
management state. The default value may be changed by
auto-loading from EEPROM.
26
D2 Power State
Support
RO
Read as 1b to indicate the I/O bridge supports the D2 power
management state. The default value may be changed by
auto-loading from EEPROM.
13-0093
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