PI7C9X7954
PCI Express Quad UART
Datasheet
Page 51 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
7.2. Registers in Memory-Mapping Mode
Each UART channel has a dedicated 512-byte register block in Memory mode. The register block can be
accessed by the UART Memory Base Address, which is obtained by adding the UART Register Offset to
the content of the Base Address Register 1 (BAR1). The following diagram shows the arrangement of
individual UART register blocks.
0000h
UART0 Registers
0200h
UART1 Registers
0400h
UART2 Registers
UART3 Registers
0E00h
UART Memory Base Address
(BAR1 + UART Register Offset)
UART Register Offset
Figure 7-2
UART Register Block Arrangement in Memory Mode
Table 7-3 UART Base Address in Memory Mode
UART
UART I/O Base Address
UART0
BAR1 + 0000h
UART1
BAR1 + 0200h
UART2
BAR1 + 0400h
UART3
BAR1 + 0E00h
13-0093