PI7C9X7954
PCI Express Quad UART
Datasheet
Page 53 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
7.2.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Tx Holding
WO
When data are written to the Transmit Holding Register (THR),
they are written to the bottom of the transmitter’s associated
FIFOs, which holds a queue of data to be transmitted by the
transmitter.
Data written to the THR when the FIFOs are full are lost. The
Line Status Register (LSR) indicates the full or empty status of
the FIFOs.
Reset to 00h.
7.2.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h
BIT
FUNCTION
TYPE
DESCRIPTION
0
Rx Data Available
Interrupt
RW
0b: Disable the Receive Data Ready Interrupt
1b: Enable the Receive Data Ready Interrupt
Reset to 0b.
1
Tx Empty Interrupt
RW
0b: Disable the Transmit Holding Register Empty Interrupt
1b: Enable the Transmit Holding Register Empty Interrupt
Reset to 0b.
2
Rx Error Status
RW
0b: Disable the Receive Line Status Interrupt
1b: Enable the Receive Line Status Interrupt
Reset to 0b.
3
Modem Status
Interrupt
RW
0b: Disable the Modem Status Register Interrupt
1b: Enable the Modem Status Register Interrupt
Reset to 0b.
4
Xoff/Special
character interrupt
RW
0b: Disable the Software Flow Control Interrupt
1b: Enable the Software Flow Control Interrupt
Reset to 0b.
5
RTS Interrupt
RW
0b: Disable RTS/DTR Interrupt
1b: Enable RTS/DTR Interrupt
Reset to 0b.
6
CTS Interrupt
RW
0b: Disable CTS/DSR interrupt
1b: Enable CTS/DSR interrupt
Reset to 0b.
7
Reserved
RW
Reset to 0b.
7.2.4.
INTERRUPT STATUS REGISTER – OFFSET 02h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Interrupt Status
RO
0b: An interrupt is pending
1b: No interrupt pending
Reset to C1h.
Priority
Level
Interrupt Status Bits
Interrupt Source
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
Rx data error
2
1
0
1
0
Rx data available
3
1
0
1
0
Rx time-out
4
1
0
1
0
Tx FIFO empty
5
1
0
Modem status change
13-0093