Pericom Semiconductor BIT FUNCTION TYPE DESCRIPTION 22:18 VPD " />
參數(shù)資料
型號: PI7C9X7954AFDE
廠商: Pericom
文件頁數(shù): 26/70頁
文件大?。?/td> 0K
描述: IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: PCIe至UART橋接
接口: 高級配置電源接口(ACPI)
電源電壓: 1.8V, 3.3V
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 32 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
22:18
VPD Address
RW
Contains DWORD address that is used to generate read or write
cycle to the VPD table stored in EEPROM.
Reset to 00000b.
31:23
Reserved
RO
Read as 000h.
6.2.31. VPD DATA REGISTER – OFFSET A0h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
VPD Data
RW
When read, it returns the last data read from VPD table at the
location as specified in VPD Address.
When writes, it places the current data into VPD table at the location
as specified in VPD Address.
Reset to 00000000h.
6.2.32. VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 09h to indicate that these are Vendor Specific capability
registers.
6.2.33. NEXT ITEM POINTER REGISTER – OFFSET A4h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
The pointer points to the PCI Express capability register (E0h).
Reset to E0h.
6.2.34. LENGTH REGISTER – OFFSET A4h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Length Information
RO
The length field provides the information for number of bytes in the
capability structure (including the ID and Next pointer bytes).
Reset to 28h.
6.2.35. XPIP CSR0 – OFFSET A8h (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Reserved
RW
Reset to 04001060h.
6.2.36. XPIP CSR1 – OFFSET ACh (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Reserved
RW
Reset to 004000271h.
6.2.37. REPLAY TIME-OUT COUNTER – OFFSET B0h
BIT
FUNCTION
TYPE
DESCRIPTION
11:0
User Replay Timer
RW
A 12-bit register contains a user-defined value. The default value
may be changed by auto-loading from EEPROM.
Reset to 000h.
13-0093
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