Pericom Semiconductor BIT FUNCTION TYPE DESCRIPTION 5 DSR RO 0" />
參數(shù)資料
型號: PI7C9X7954AFDE
廠商: Pericom
文件頁數(shù): 53/70頁
文件大?。?/td> 0K
描述: IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: PCIe至UART橋接
接口: 高級配置電源接口(ACPI)
電源電壓: 1.8V, 3.3V
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 57 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
5
DSR
RO
0b: The DSR input state is the logic 0
1b: The DSR input state is the logic 1
Reset to 0b.
6
RI
RO
The input state of RI pin
Reset to 0b.
7
DCD
RO
The input state of DCD pin
Reset to 0b.
7.2.10. SPECIAL FUNCTION REGISTER – OFFSET 07h
BIT
FUNCTION
TYPE
DESCRIPTION
0
Force Transmission
RW
Forces transmitter to always to transmit data.
1b: Enabled
0b: Disabled
Reset to 0b.
1
Auto DSR and
DTR Flow Control
RW
Auto DSR and DTR flow control enable
1b: Enables DSR and DTR auto flow control
0b: Disables DSR and DTR auto flow control
Reset to 0b.
2
Reserved
RO
Reset to 0b.
3
Reserved
RO
Reset to 0b.
4
Reserved
RW
Reset to 0b.
5
950 Mode
RW
1b: Enables 950 mode
0b: Non-950 mode
Reset to 0b.
6
RFD / LSR
Counter Select
RW
1b: OFFSET 15 bit[7:0] acts as the Line Status Register Counter
0b: OFFSET 15 bit[7:0] acts as the Receive FIFO Data Counter
Reset to 0b.
7
TFD / SCR Select
RW
1b: OFFSET 16 bit[7:0] acts as the Transmit FIFO Data Counter
0b: OFFSET 16 bit[7:0] acts as the Sample Clock Register
Reset to 0b.
7.2.11. DIVISOR LATCH LOW REGISTER – OFFSET 08h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Divisor Low
RW
Lower-part of the divisor register
Reset to 00h.
7.2.12. DIVISOR LATCH HIGH REGISTER – OFFSET 09h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Divisor High
RW
Higher-part of the divisor register
Reset to 00h.
7.2.13. ENHANCED FUNCTION REGISTER – OFFSET 0Ah
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
In-Band Receive
Flow Control Mode
RW
When in-band receive flow control is enabled, the UART
compares the received data with the programmed XOFF
13-0093
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