PI7C9X7954
PCI Express Quad UART
Datasheet
Page 12 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
4.2. PIN DESCRIPTION
4.2.1.
UART INTERFACE
PIN NO.
NAME
TYPE
DESCRIPTION
119, 87, 79,
71
SOUT [3:0]
O
UART Serial Data Outputs: The output pins transmit serial data
packets with start and end bits. SOUT[0] and SOUT[1] are output
signals with weak internal pull-down resistors.
122, 90, 82,
74
SIN [3:0]
I
UART Serial Data Inputs: The input pins receive serial data
packets with start and end bits. The pins are idle high.
126, 94, 86,
78
DCD [3:0]
I
Modem Data-Carrier-Detect Input and General Purpose Input
(Active Low)
121, 89, 81,
73
DTR [3:0]
O
Modem Data-Terminal-Ready Output (Active LOW): If
automated DTR# flow control is enabled, the DTR# pin is asserted
and deasserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively. DTR[0] and DTR[1] are
output signals with weak internal pull-down resistors.
120, 88, 80,
*72
RTS [3:0]
O
Modem Request-To-Send Output (Active LOW): If automated
RTS# flow control is enabled, the RTS# pin is deasserted and
reasserted whenever the receiver FIFO reaches or falls below the
programmed thresholds, respectively. RTS[0] and RTS[1] are output
signals with weak internal pull-down resistors.
EEPROM Bypass: During system initialization, RTS[0] acts as the
EEPROM Bypass pin, and it is used to bypass EEPROM
pre-loading. The pin is active-high. When it is asserted at start-up,
the EEPROM pre-loading is bypassed, and no configuration data is
loaded from the EEPRPOM. Otherwise, configuration data is loaded
from the EEPROM.
123, 91, 83,
75
CTS [3:0]
I
Modem Clear-To-Send Input (Active LOW): If automated CTS#
flow control is enabled, upon deassertion of the CTS# pin, the
transmitter will complete the current character and enter the idle
mode until the CTS# pin is reasserted. Note: flow control characters
are transmitted regardless of the state of the CTS# pin.
124, 92, 84,
76
DSR [3:0]
I
Modem Data-Set-Ready Input (Active LOW): If automated
DSR# flow control is enabled, upon deassertion of the DSR# pin,
the transmitter will complete the current character and enter the idle
mode until the DSR# pin is reasserted. Note: flow control characters
are transmitted regardless of the state of the DSR# pin.
125, 93, 85,
77
RI [3:0]
I
Modem Ring-Indicator Input (Active LOW)
7
XTLO
O
Crystal Oscillator Output
6
XTLI
I
Crystal Oscillator Input Or External Clock Pin: The maximum
frequency supported by this device is 60MHz.
*52, *51, 50,
*49
DRIVER_SEL0
[3:0]
O
DRIVER_SEL0: Used to select RS-232/ RS-424/ 4-Wire RS-485/
2-Wire RS-458 Serial Port Mode for UART 0. DRIVER_SEL0 [3:0]
are output signals with weak internal pull-down resistors.
Driver Current Level Control (DTX[0]): During system
initialization, DRIVER_SEL0[3] acts as the DTX[0] pin, and it is
used to control the driver current level. By default, it is set to ‘0’
without pin strapped.
Low Driver Control (LO_DRV): During system initialization,
DRIVER_SEL0[2] acts as the LO_DRV pin, and it is used to
decrease the nominal value of the PCI Express lane’s driver current
level. By default, it is set to ‘0’ without pin strapped.
High Driver Control (HI_DRV): During system initialization,
DRIVER_SEL0[0] acts as the HI_DRV pin, and it is used to
increase the nominal value of the PCI Express lane’s driver current
level. By default, it is set ‘0’ without pin strapped.
13-0093