Pericom Semiconductor EEPROM ADDRESS PCIE REGISTER OFFSET DEFA" />
參數(shù)資料
型號: PI7C9X7954AFDE
廠商: Pericom
文件頁數(shù): 61/70頁
文件大?。?/td> 0K
描述: IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: PCIe至UART橋接
接口: 高級配置電源接口(ACPI)
電源電壓: 1.8V, 3.3V
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 64 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
EEPROM
ADDRESS
PCIE REGISTER OFFSET
DEFAULT
Value
DESCRIPTION
14h
Offset B4h bit[31:16]
0000h
UART Transmitter Drive Enable:
RS232/422/485-2W/485-4W Selection for UART 4
to 7
16h
Bit[1:0] - Offset B8h bit[17:16]
01b
PM Control Parameter: Determines whether this
bridge enters L1 or not when D3 condition occurs.
Bit[3:2] - Offset B8h bit[19:18]
00b
PM Control Parameter: Determines the delay
counter value when entering L1
Bit[5:4] - Offset B8h bit[21:20]
00b
PM Control Parameter: Determines whether this
bridge asserts L0s/L1 handshake protocol
18h
Bit[13:0] - Offset C8h bit[13:0]
0200h
PHY Parameter
1Ah
Bit[0] - Offset C4h bit[15]
1b
Role Based Error Report Enable: Indicates
implement the role-base error reporting
Bit[15:8] - Offset 34h bit[7:0]
80h
Capability List Pointer: Points to a linked list of
new capabilities implemented by the device
1Ch
[7:0] - Offset 08h bit[7:0]
00h
Revision ID: Indicates revision number of device
40h
12D8h
Check Code
13-0093
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