Pericom Semiconductor The receiver writes data to the bottom o" />
參數(shù)資料
型號(hào)： PI7C9X7954AFDE
廠商： Pericom
文件頁數(shù)： 13/70頁
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級(jí)配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 20 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
The receiver writes data to the bottom of the RHR when it finishes receiving and decoding the data bits. If
the RHR is full when the receiver attempts to write data to it, a data overrun occurs. Any read operation to
an empty RHR is invalid.
The empty and full status of the THR and RHR can be determined by reading the empty and full flags in
the Line Status Register (LSR). When the transmitter and receiver are ready to transfer data to and from the
FIFOs, interrupts are raised to signal this condition. Additionally, the user can use the Receive FIFO Data
Counter (RFDC) and Transmit FIFO Data Counter (TFDC) registers to determine the number of items in
each FIFO.
DATA0
DATA1
DATA2
UART COMMON MODE
ADDRESS
PCI EXPRESS MASTER
RHR
LSR
THR
DATA125
DATA126
DATA127
LSR0
LSR1
LSR2
LSR125
LSR126
LSR127
DATA0
DATA1
DATA2
DATA125
DATA126
DATA127
RP
WP
RP
WP
Figure 5-1 Transmit and Receive FIFOs
13-0093
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