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| 型號(hào)： | PM7351 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | OCTAL SERIAL LINK MULTIPLEXER |
| 中文描述： | 八路串行連接復(fù)用器 |
| 文件頁(yè)數(shù)： | 140/174頁(yè) |
| 文件大?。?/td> | 1790K |
| 代理商： | PM7351 |
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RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
130
12.2 Interaction Between Bus and LVDS Configurations
Since the far-end and near-end devices are configured independently it is
important to take into account how the optional fields (the Any-PHY address field,
the H5/UDF header bytes, and the user prepend word) are treated on an end-to-
end basis. The following table summarizes the possible cell format options and
summarizes the resultant impact on the cell contents at the receiving end.
Note the following:
In general the S/UNI-VORTEX’s LVDS links will be connected to S/UNI-
DUPLEX devices. Hence the far end registers would normally reside in the
S/UNI-DUPLEX device. However, there is nothing preventing a S/UNI-
VORTEX from being connected to another S/UNI-VORTEX over the LVDS
connection. Therefore, the following tables identify register appropriate for a
S/UNI-VORTEX to S/UNI-VORTEX connection. The results are similar for a
S/UNI-VORTEX to S/UNI-DUPLEX connection except the S/UNI-DUPLEX
can function as a true Utopia L2 bus master or bus slave. Refer to the
S/UNI-DUPLEX datasheet for details.
The downstream bus (from bus master to S/UNI-VORTEX) can only operate
in Any-PHY mode, meaning Any-PHY bus timing and addressing must be
used. However, if the Downstream Cell Interface Configuration register
(0x008) is set such that the PHY address is mapped into the H5/UDF field
(INADDUDF = 1) then the minimum length cell can be 54 bytes long rather
than Any-PHY’s default 56 byte cell.
The upstream bus can be configured as SCI-PHY (Input pin RANYPHY = 0)
or Any-PHY (RANYPHY = 1). Setting the INADDUDF bit of register 0x00C to
1 when the bus is configured as Any-PHY has no effect. However, in SCI-
PHY mode setting the INADDUDF bit of register 0x00C to 1 and the
PREPEND bit to 0 ensures the upstream bus is Utopia L2 compliant.
For control cells written or read via the microprocessor port, bytes 0&1
correspond to the microprocessor port’s unique PHY address field. However
since this field is fixed there is no useful information in these bytes. Bytes
10&11 are always undefined. Bytes 2&3 correspond to the user prepend
bytes, and bytes 8&9 correspond to the H5&HDF bytes. Control cells
transferred across the SCI-PHY/Any-PHY buses are formatted like all other
cells.
The PHY address field is transported across the LVDS in an extra word
added to each user cell. Therefore it is not necessary that the H5/UDF field
be sent over the LVDS link
even if the bus interfaces are configured to
embed the PHY address in the H5/UDF fields
. This will slightly increase
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相關(guān)代理商/技術(shù)參數(shù) |
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| PM7351-BI | 制造商:PMC 制造商全稱:PMC 功能描述:OCTAL SERIAL LINK MULTIPLEXER |
| PM-736 | 制造商:Eclipse Tools 功能描述: |
| PM7364 | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER |
| PM7364-BI | 制造商:PMC-Sierra 功能描述:PROTOCOL CONTROLLER, 256 Pin, BGA |
| PM7366 | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER |
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