參數(shù)資料
型號(hào): PM7351
廠商: PMC-Sierra, Inc.
英文描述: OCTAL SERIAL LINK MULTIPLEXER
中文描述: 八路串行連接復(fù)用器
文件頁數(shù): 29/174頁
文件大?。?/td> 1790K
代理商: PM7351
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
19
Ball
Name
Type
Ball
No.
Function
RDAT[15]
RDAT[14]
RDAT[13]
RDAT[12]
RDAT[11]
RDAT[10]
RDAT[9]
RDAT[8]
RDAT[7]
RDAT[6]
RDAT[5]
RDAT[4]
RDAT[3]
RDAT[2]
RDAT[1]
RDAT[0]
Output
A20
C19
D19
D21
C23
D22
E21
D23
E22
F21
G20
E23
F22
G21
H20
G23
The receive cell data bus (RDAT[15:0]) carries the
ATM cell words that have been read from the S/UNI-
VORTEX internal cell buffers.
The RDAT[15:0] bus is updated on the rising edge of
RCLK and considered valid only when the S/UNI-
VORTEX device was selected after the polling
process and the RENB signal is sampled low. If
RANYPHY is logic low RDAT[15:0] is driven
immediately upon sampling RENB low, but it has an
additional cycle latency when RANYPHY is logic high.
RDAT[15:0] becomes high impedance upon sampling
RENB high or if the S/UNI-VORTEX device is not
selected for transfer.
When RANYPHY is high, autonomous deselection
occurs after the last word of a cell resulting in setting
RDAT[15:0] high-impedance until reselection.
RPRTY
Output
B19
The Receive Parity (RPRTY) signal completes the
parity (programmable for odd or even parity) of the
RDAT[15:0] bus.
The RPRTY signal is updated on the rising edge of
RCLK and is considered valid only when the S/UNI-
VORTEX device was selected after the polling
process and the RENB signal is sampled low. If
RANYPHY is logic low RPRTY is driven immediately
upon sampling RENB low, but it has an additional
cycle latency when RANYPHY is logic high. RPRTY
becomes high impedance upon sampling RENB high
or if the S/UNI-VORTEX device is not selected for
transfer.
When RANYPHY is high, autonomous deselection
occurs after the last word of a cell resulting in setting
RPRTY high-impedance until reselection.
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