參數(shù)資料
型號: PM7351
廠商: PMC-Sierra, Inc.
英文描述: OCTAL SERIAL LINK MULTIPLEXER
中文描述: 八路串行連接復(fù)用器
文件頁數(shù): 81/174頁
文件大?。?/td> 1790K
代理商: PM7351
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
71
Register 0x00C: Upstream Cell Interface Configuration and Interrupt Status
Bit
Type
Function
Default
Bit 7
R
CELLXFERRI
X
Bit 6
R/W
CELLXFERRE
0
Bit 5
Unused
X
Bit 4
R/W
INADDUDF
0
Bit 3
R/W
H5UDF
1
Bit 2
R/W
Reserved
0
Bit 1
R/W
PREPEND
0
Bit 0
R/W
PTYP
0
PTYP:
The Parity Type (PTYP) bit selects even or odd parity for the RPRTY output.
When set to logic 1, RPRTY completes even parity bit for RDAT[15:0]. When
set to logic 0, RPRTY completes odd parity bits for RDAT[15:0].
PREPEND:
The PREPEND bit determines whether a word is prepended to each cell.
When PREPEND is logic 1, the optional “Word 1” illustrated in Fig. 3 (p. 34)
is included in the data structure presented on RDAT[15:0].
Reserved:
This bit must be logic 0 for correct operation.
H5UDF:
The H5UDF bit determines whether or not the H5/UDF octets are included in
cells transferred over the interface. When H5UDF is logic 1 (default), the H5
and UDF octets are included, i.e. the optional “Word 4” illustrated in Fig. 3 (p.
32) is included in the data structure presented on RDAT[15:0].
INADDUDF:
The INADDUDF (inband addressing in UDF byte) bit re-locates the inband
address. When this bit is set, the logical channel address for in band
selection is located in the fourteen lower bits of the H5 and UDF bytes and
there is no extended address word in front of the prepend word. This bit
supercedes the H5UDF bit, in that it forces the inclusion of “Word 4”. This bit
has no effect if the RANYPHY input is logic 1.
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