- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378056 > PM7351 (PMC-Sierra, Inc.) OCTAL SERIAL LINK MULTIPLEXER PDF資料下載
參數(shù)資料
| 型號： | PM7351 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | OCTAL SERIAL LINK MULTIPLEXER |
| 中文描述： | 八路串行連接復(fù)用器 |
| 文件頁數(shù)： | 56/174頁 |
| 文件大?。?/td> | 1790K |
| 代理商： | PM7351 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
46
master as a single cell stream. Scheduling from the S/UNI-VORTEX onto the
upstream bus is described more fully in Section 9.1.2 on Page 32.
In aggregate, the 8 upstream links can burst data into the S/UNI-VORTEX at up
to 1.6 Gbps, which is twice the maximum bandwidth of the upstream bus.
Further, the bus master may be servicing several S/UNI-VORTEX devices at
once or be otherwise restricted in the maximum sustained bandwidth it is able to
receive from the S/UNI-VORTEX. Therefore, the potential to overflow one or
more of the 6 cell upstream FIFOs is a real possibility.
When any upstream FIFO has less than three empty cell buffers, it deasserts the
cell available (CA[0]) bit sent in the system overhead of the corresponding
downstream LVDS link (see Table 2). It is the responsibility of the far end device
(typically a S/UNI-DUPLEX) to start sending stuff cells immediately upon
indication that the S/UNI-VORTEX can accept no more traffic. By setting the full
mark at 3 cells the S/UNI-VORTEX allows for up to two additional cells can be
accepted after the cell available bit is deasserted. This accommodates far-end
latency in reaction to the CA[0] indication.
9.4 Timing Reference Insertion and Recovery
The high-speed LVDS links are capable of transporting a timing reference in both
directions, independent of the LVDS bit rate. As shown in Table 2, every cell
transmitted over the LVDS contains a timing reference field called TREF[5:0].
Although the timing reference is targeted at a typical need of transporting an 8
kHz signal, its frequency is not constrained to 8 kHz. Any frequency less than
the cell rate is permissible.
In the transmit direction, rising edges on the TX8K input are encoded in the cells
transmitted on all eight serial links. For each of the 8 LVDS links, the rising edge
of TX8K causes an internal counter to be initialized to the cell length minus 1.
The counter decrements with each subsequent byte transmitted until the fourth
byte of the next extended cell, at which point the state of the counter is written
into the outgoing TREF[5:0] field. If no rising edge on TX8K has occurred,
TREF[5:0] is set to all ones.
In the receive direction the S/UNI-VORTEX is typically receiving cells from a
S/UNI-DUPLEX device, which implements the same TX8K process described
above. As determined by the value of the RX8KSEL[2:0] bits in the Master
Configuration register, the timing signal received over one of the eight LVDS links
is recreated on RX8K.
The S/UNI-VORTEX monitors the TREF[5:0] field on the selected upstream
LVDS link and initializes an internal counter to the value of TREF[5:0] each time
the field is received. The counter decrements with each subsequent byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM7351-BI | OCTAL SERIAL LINK MULTIPLEXER |
| PM7364 | Frame Engine and Datalink Manager |
| PM7364-BI | FRAME ENGINE AND DATA LINK MANAGER |
| PM7366 | FRAME ENGINE AND DATA LINK MANAGER |
| PM7366-BI | TVS BI-DIR 30V 1500W DO-201 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM7351-BI | 制造商:PMC 制造商全稱:PMC 功能描述:OCTAL SERIAL LINK MULTIPLEXER |
| PM-736 | 制造商:Eclipse Tools 功能描述: |
| PM7364 | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER |
| PM7364-BI | 制造商:PMC-Sierra 功能描述:PROTOCOL CONTROLLER, 256 Pin, BGA |
| PM7366 | 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。