參數(shù)資料
型號： PM7351
廠商： PMC-Sierra, Inc.
英文描述： OCTAL SERIAL LINK MULTIPLEXER
中文描述： 八路串行連接復(fù)用器
文件頁數(shù)： 142/174頁
文件大?。?/td> 1790K
代理商： PM7351
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
132
Near end
downstream
Reg 0x0008
Far-end
upstream
Reg 0x00C
LVDS:
both ends
must match
e.g. Reg
0x080 and
0x90
U
S
R
H
D
R
N
D
Resultant Cell contents at far-end Bus or Microprocessor
H
5
U
D
F
I
N
A
D
D
U
D
F
P
R
E
P
E
N
D
H
5
U
D
F
I
N
A
D
D
U
D
F
P
R
E
P
E
N
D
P
R
E
P
E
C
E
L
L
C
R
C
Note: USRHDR is a two bit value that defines the number of
header bytes transferred over the LVDS link.
00 = 4 bytes
01 = 5 bytes (UDF not sent)
10 = 6 bytes (default)
11 = reserved
Note: The LVDS transmitter adds 5 overhead bytes to every
cell, which includes room for PHY address information. Thus
the LVDS cell format is the same whether the PHY address
arrives as a prepend or embedded in the H5/UDF field.
At the far-end the H5 & UDF bytes contain the PHY
address, and neither an address field nor a cell prepend
exist.
Control cell prepend bytes 2&3 are undefined, header
bytes 8&9 are valid at far-end microprocessor. If the
control cell came from the downstream bus bytes 8&9
have no useful information (just the microprocessor port’s
PHY ID). If the control cell came from the
microprocessor then bytes 8&9 will contain the value sent
(i.e. they are not overwritten by the PHY ID)
THIS CONFIGURATION NOT VALID IF RANYPHY = 1
58 byte user cells (5 header bytes, UDF is removed) are
transferred from a 54 byte bus to a 54 byte bus.
At the far-end bus the H5 & UDF bytes contain the PHY
address, and neither an address field (Word 0) nor a
prepend exist.
Control cell prepend bytes 2&3 and header byte 9 are
undefined at the Rx end. If the cell came from the
microprocessor port then header byte 8 is what was
written. However, if the cell came from the bus then byte
8 is just half of the PHY ID value, and hence contains no
useful information.
THIS CONFIGURATION NOT VALID IF RANYPHY = 1
57 byte user cells (4 header bytes, H5/UDF are
removed) are transferred from a 54 byte bus to a 54 byte
bus.
At the far-end bus the H5 & UDF bytes contain the PHY
address, and neither an address field (Word 0) nor a
prepend exist.
At the far end the control cell prepend bytes 2&3 and
header bytes 8&9 are undefined regardless of source of
the cell.
61 byte cells (5 system, 2 prepend, 6 header, 48 data
bytes) are transferred from a 58 byte bus to a 58 byte
bus.
Prepend, PHY address and H5 & UDF bytes are valid.
Control cell prepend bytes 2&3 and header bytes 8&9
are valid at far-end microprocessor.
X
1
0
X
1
0
5
0
0
X
1
0
X
1
0
4
0
0
1
0
1
1
0
1
6
1
0
相關(guān)PDF資料
PDF描述
PM7351-BI OCTAL SERIAL LINK MULTIPLEXER
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PM7364-BI FRAME ENGINE AND DATA LINK MANAGER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PM7351-BI 制造商:PMC 制造商全稱:PMC 功能描述:OCTAL SERIAL LINK MULTIPLEXER
PM-736 制造商:Eclipse Tools 功能描述:
PM7364 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER
PM7364-BI 制造商:PMC-Sierra 功能描述:PROTOCOL CONTROLLER, 256 Pin, BGA
PM7366 制造商:PMC 制造商全稱:PMC 功能描述:FRAME ENGINE AND DATA LINK MANAGER
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