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參數(shù)資料
| 型號(hào)： | PM7351 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | OCTAL SERIAL LINK MULTIPLEXER |
| 中文描述： | 八路串行連接復(fù)用器 |
| 文件頁(yè)數(shù)： | 141/174頁(yè) |
| 文件大?。?/td> | 1790K |
| 代理商： | PM7351 |
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RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
131
the effective throughput of the LVDS, but it will impact control cells inserted
and extracted via the microprocessor port as described in section 12.5.
Some valid combinations are not shown in Table 5. Some of the missing
combinations are readily derived from the table. Other combinations make
little sense. For example, there is no use sending prepend information over
the LVDS link if the receiving bus is not configured for prepends. Even if the
near-end bus is configured for prepend it is more bandwidth efficient to turn
off prepend on the LVDS link (the default setting) and hence discard the
prepend at the near-end bus interface.
Table 5 From near-end downstream bus to far-end upstream bus
Near end
downstream
Reg 0x0008
Far-end
upstream
Reg 0x00C
LVDS:
both ends
must match
e.g. Reg
0x080 and
0x90
U
S
R
H
D
R
N
D
Resultant Cell contents at far-end Bus or Microprocessor
H
5
U
D
F
I
N
A
D
D
U
D
F
P
R
E
P
E
N
D
H
5
U
D
F
I
N
A
D
D
U
D
F
P
R
E
P
E
N
D
P
R
E
P
E
C
E
L
L
C
R
C
Note: USRHDR is a two bit value that defines the number of
header bytes transferred over the LVDS link.
00 = 4 bytes
01 = 5 bytes (UDF not sent)
10 = 6 bytes (default)
11 = reserved
Note: The LVDS transmitter adds 5 overhead bytes to every
cell, which includes room for PHY address information. Thus
the LVDS cell format is the same whether the PHY address
arrives as a prepend or embedded in the H5/UDF field.
THIS IS THE DEFAULT CONFIGURATION
59 byte cells (5 system, 6 header bytes, 48 data bytes)
are transferred from a 56 byte bus to a 56 byte bus.
At the far-end bus, the address and H5 & UDF bytes are
valid, and a cell prepend does not exist.
Control cell prepend bytes 2&3 are undefined, header
bytes 8&9 are valid at far-end microprocessor.
58 byte cells (5 header bytes, UDF is removed) are
transferred from a 56 byte bus to a 56 byte bus.
At the far-end bus, H5 is valid, UDF is undefined, and a
cell prepend does not exist.
Control cell prepend bytes 2&3 and header byte 9 are
undefined at Rx. Header byte 8 is defined.
57 byte cells (4 header bytes, H5&UDF are removed) are
transferred from a 56 byte bus to a 56 byte bus.
At the far-end bus, the PHY address is valid, and H5 &
UDF exist but are undefined. A cell prepend does not
exist.
Control cell prepend bytes 2&3 and header bytes 8&9
are undefined at far-end microprocessor.
THIS CONFIGURATION NOT VALID IF RANYPHY = 1
59 byte cells (6 header bytes) are transferred from a 54
byte bus to a 54 byte bus.
1
0
0
1
0
0
6
0
0
1
0
0
1
0
0
5
0
0
1
0
0
1
0
0
4
0
0
X
1
0
X
1
0
6
0
0
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