PEB 20560
Functional Block Description
Semiconductor Group
2-154
2003-08
2.14.1.9
Scratchpad Register (SCR)
This 8-bit read/write register does not control the UART in any way. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
2.14.2
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FEWO = 1, ERBFI = 1)
RCVR interrupts will occur as follows:
a) The receive data available interrupt will be issued to the
μ
P when the FIFO has
reached its programmed trigger level; it will be cleared as soon as the FIFO drops
below its programmed trigger level.
b) The IIR receive data available indication also occurs when the FIFO trigger level is
reached, and like the interrupt it is cleared when the FIFO drops below the trigger
level.
c) The receiver line status interrupt (IIR = 06), as before, has higher priority than the
received data available (IIR = 04) interrupt.
d) The data ready bit (DR) is set as soon as a character is transferred from the shift
register to the RCVR FIFO. It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts
will occur as follows:
a) A FIFO time-out interrupt will occur, if the following conditions exist:
– at least one character is in the FIFO
– the most recent serial character received was longer than 4 continuous character
times ago (if 2 stop bits are programmed the second one is included in this time
delay).
– the most recent
μ
P read of the FIFO was longer than 4 continuous character
times ago.
This will cause a maximum character received to interrupt issued delay of
160 ms at 300 Baud with a 12-bit character.
b) Character times are calculated by using the RCLK input for a clock signal (this
makes the delay proportional to the baudrate).
c) When a time-out interrupt has occurred it is cleared and the timer reset when the
μ
P reads one character from the RCVR FIFO.
d) When a time-out interrupt has not occurred the time-out timer is reset after a new
character is received or after the
μ
P reads the RCVR FIFO.
bit
SCR
7
0
X
X
X
X
X
X
X
X