PEB 20560
DSP Core OAK
Semiconductor Group
4-3
2003-08
4.2
Architecture Features
4.2.1
Features
16-bit fixed-point DSP CORE with high level of modularity:
– Expandable internal program ROM.
– Expandable internal data RAM and/or ROM.
– User-defined registers.
16
×
16 bit 2’s complement parallel multiplier with 32-bit product. Multiplication of
signed by signed, signed by unsigned, and unsigned by unsigned.
Single cycle multiply-accumulate instructions.
36-bit ALU.
36-bit left/right Barrel Shifter.
Four 36-bit accumulators.
Memory organization:
64 K word maximum addressable data space, organized in:
local and external data memory space.
– 64 K word maximum program memory space.
– Data RAMs can also be viewed as a single continuous RAM.
– User definable data ROM on the same address space of the data RAM.
– Alternative registers bank for 3 of the DAAU pointers (and 1 configuration register)
with individual selectable bank exchanging.
Software stack (with stack pointer) residing in the data RAM.
Index-based addressing capability.
Automatic context switching by interrupts (with enable/disable feature for each
interrupt) using Shadow registers for parts of status registers and swapping between
two 36-bit accumulators.
All general and most special purpose registers are arranged as a global register set
of 34 registers that can be referenced in most data moves and core operations.
Bit-Field (up to 16 bits) Operations (BFO): Set, Reset, Change, Test.
These operations are executed directly on registers and data memory content, with
no affect on accumulators’ content.
Single cycle exponent evaluation of up to 36-bit values.
Enables full normalization operation in 2 cycles.
Double precision multiplication support.
Max/Min single cycle instruction with pointer latching and modification.
Optimized for codebook search and Viterbi decoding.
Single cycle Division step support.
Single cycle data move & shift capability.
Arithmetic and logical shifting capability, according to a shift value stored in a special
register, or embedded in the instruction opcode. Conditional shift is also available, as
well as rotate left and right operations.