參數(shù)資料
型號(hào)： RM7065A-400T
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 18/52頁(yè)
文件大小： 901K
代理商： RM7065A-400T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
18
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
4.10 System Control Coprocessor (CP0)
The system control coprocessor (CP0) is responsible for the virtual memory sub-system, the
exception control system, and the diagnostics capability of the processor.
For memory management support, the RM7065A CP0 is logically identical to the RM5200
Family. For interrupt exceptions and diagnostics, the RM7065A is a superset of the RM5200
Family, implementing additional features described in the following sections on Interrupts, Test/
Breakpoint registers, and Performance Counters.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer (ITLB) a data address translation buffer (DTLB), a Joint TLB
(JTLB), and coprocessor registers used by the virtual memory mapping sub-system.
4.11 System Control Coprocessor Registers
The RM7065A incorporates all CP0 registers internally. These registers provide the path through
which the virtual memory system’s page mapping is examined and modified, exceptions are
handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled,
cache features). In addition, the RM7065A includes registers to implement a real-time cycle
counting facility, to aid in cache and system diagnostics, and to assist in data error detection.
To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7065A,
both the data and control register spaces of CP0 are supported. In the data register space, which is
accessed using the
MFC0
and
MTC0
instructions, the RM7065A supports the same registers as
found in the RM5200 Family. In the control space, which is accessed by the previously unused
CTC0
and
CFC0
instructions, the RM7065A supports five new registers. The first three of these
new 32-bit registers support the enhanced interrupt handling capabilities; Interrupt Control,
Interrupt Priority Level Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI). These registers are
described further in the section on interrupt handling. Two other registers, Imprecise Error 1 and
Imprecise Error 2, have been added to help diagnose bus errors that occur on non-blocking
memory references.
Figure 5 shows the CP0 registers.
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