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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
31
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
4.30 Enhanced Write Modes
The RM7065A implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write on the
SysAD
bus every four
SysClock
cycles. Hence for a non-block write, this meant that two out of every four cycles were
wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous data cycle. This allows for higher
SysAD
bus utilization. However, at high frequencies the processor may drive a subsequent write
onto the bus prior to the time the external agent deasserts
WrRdy*
, indicating that it can not
accept another write cycle. This can cause the cycle to be aborted.
Write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue
aborted write cycles. If
WrRdy*
is deasserted during the issue phase of a write operation, the
cycle is aborted by the processor and reissued at a later time.
In write reissue mode, a rate of one write every two bus cycles can be achieved. Pipelined writes
have the same two bus cycle write repeat rate, but can issue one additional write following the
deassertion of
WrRdy*
.
4.31 External Requests
The RM7065A can respond to certain requests issued by an external device. These requests take
one of two forms:
Write
requests and
Null
requests. An external device executes a
write
request
when it wishes to update one of the processors writable resources such as the internal interrupt
register. A
null
request is executed when the external device wishes the processor to reassert
ownership of the processor external interface. Once the external device has acquired control of the
processor interface via
ExtRqst*
, it can execute a null request after completing an independent
transaction between itself and system memory in a system where memory is connected directly to
the
SysAD
bus. Normally this transaction would be a DMA read or write from the I/O system.
4.32 Test/Breakpoint Registers
To facilitate hardware and software debugging, the RM7065A incorporates a pair of Test/Break-
point, or Watch registers, called Watch1 and Watch2. Each Watch register can be separately
enabled to watch for a load address, a store address, or an instruction address. All address
comparisons are done on physical addresses. An associated register, Watch
Mask, has also been
added so that either or both of the Watch registers can compare against an address range rather
than a specific address. The range granularity is limited to a power of two.
When enabled, a match of either Watch register results in an exception. If the Watch is enabled for
a load or store address then the exception is the Watch exception as defined for the R4000 by
Cause exception code twenty-three. If the Watch is enabled for instruction addresses then a newly
defined
Instruction Watch
exception is taken and the Cause code is sixteen. The Watch register
which caused the exception is indicated by Cause bits 25:24. Table 9 summarizes a Watch
operation.