參數(shù)資料
型號(hào)： RM7065A-400T
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 25/52頁(yè)
文件大?。?/td> 901K
代理商： RM7065A-400T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
25
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
The RM7065A cache attributes for the instruction, data, internal secondary caches are summarized
in Table 6.
Table 6 Cache Attributes
Attribute
4.21 Cache Locking
The RM7065A allows critical code or data fragments to be locked into the primary and secondary
caches. The user has complete control over the locking function. For instruction and data
fragments in the primary caches, locking is accomplished by setting either or both of the cache
lock enable bits and specifying the set in the CP0 ECC register, then executing either a load
instruction for data, or a Fill_I cache operation for instructions.
Only sets A and B within each cache can be locked. Locking within the secondary works
identically to the primaries using a separate secondary lock enable bit and the same set selection
field. As with the primaries, only sets A and B can be locked. Table 7 summarizes the cache
locking capabilities.
Instruction
Data
Secondary
Size
16KB
16KB
256KB
Associativity
4-way
4-way
4-way
Replacement
Algorithm
cyclic
cyclic
cyclic
Line size
32 byte
32 byte
32 byte
Index
vAddr
11..0
pAddr
35..12
n.a.
vAddr
11..0
pAddr
35..12
write-back,
write-through
pAddr
15..0
pAddr
35..16
block write-
back, bypass
Tag
Write policy
read policy
n.a.
non-blocking (2
outstanding)
non-blocking
(data only, 2
outstanding)
read order
critical word first
critical word first critical word
first
write order
NA
sequential
sequential
miss restart
following:
complete line
first double (if
waiting for data)
n.a.
Parity
per word
per byte
per
doubleword
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