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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
32
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
Table 9 Watch Control Register
Register
Bit Field/Function
Note that the
W1
and
W2
bits of the Cause register indicate which Watch register caused a partic-
ular Watch exception.
4.33 Performance Counters
To facilitate system tuning, the RM7065A implements a performance counter using two new CP0
registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter which
causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register containing a 5-
bit field which selects one of twenty-two event types as well as a handful of bits which control the
overall counting function. Note that only one event type can be counted at a time and that counting
can occur for user code, kernel code, or both. The event types and control bits are listed in Table
10.
63
62
61
60:36
35:2
1:0
Watch1, 2
Store
Load
Instr
0
Addr
0
31:2
1
0
Watch Mask
Mask
Mask
Watch
2
Mask
Watch
1
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