參數(shù)資料
型號(hào)： RM7065A-400T
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 36/52頁(yè)
文件大?。?/td> 901K
代理商： RM7065A-400T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
36
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
Table 15 Interrupt Vector Spacing
ICR[4..0]
4.35 Standby Mode
The RM7065A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the
WAIT
instruction enables interrupts and causes the processor to enter Standby
Mode. If the
SysAD
bus is currently idle when the WAIT instruction completes the W pipe stage,
the internal processor clock stops, thereby freezing the pipeline. The phase lock loop, or PLL,
internal timer/counter, and the "wake up" input pins:
IP[9.0]*
,
NMI*
,
ExtReq*
,
Reset*
, and
ColdReset*
continue to operate in their normal fashion.
If the
SysAD
bus is not idle when the
WAIT
instruction completes the W pipe stage, then the
WAIT
is treated as a
NOP
until the bus operation is completed. Once the processor is in Standby,
any interrupt, including the internally generated timer interrupt, causes the processor to exit
Standby and resume operation where it left off. The
WAIT
instruction is typically inserted in the
idle loop of the operating system or real time executive.
4.36 JTAG Interface
The RM7065A interface supports JTAG boundary scan in conformance with IEEE 1149.1. The
JTAG interface is useful for checking the integrity of the processor’s pin connections.
4.37 Boot-Time Options
The RM7065A operating modes are initialized at power-up by the boot-time mode control
interface. The serial boot-time mode control interface operates at a very low frequency (
SysClock
divided by 256), allowing the initialization information to be kept in a low cost EPROM or system
interface ASIC.
4.38 Boot-Time Modes
The boot-time serial mode stream is defined in Table 16. Bit 0 is presented to the processor as the
first bit in the stream when
VccOK
is de-asserted. Bit 255 is the last bit transferred.
Spacing
0x0
0x000
0x1
0x020
0x2
0x040
0x4
0x080
0x8
0x100
0x10
0x200
others
reserved
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