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參數(shù)資料

RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use

Document ID: PMC-2010145, Issue 3

List of Tables

Table 1 Instruction Issue Rules .................................................................................................12

Table 2 Dual Issue Instruction Classes .....................................................................................13

Table 3 ALU Operations ............................................................................................................15

Table 4 Integer Multiply/Divide Operations ................................................................................15

Table 5 Floating Point Latencies and Repeat Rates .................................................................17

Table 6 Cache Attributes ...........................................................................................................25

Table 7 Cache Locking Control .................................................................................................26

Table 8 Penalty Cycles ..............................................................................................................26

Table 9 Watch Control Register ................................................................................................32

Table 10 Performance Counter Control .....................................................................................33

Table 11 Cause Register ...........................................................................................................35

Table 12 Interrupt Control Register ...........................................................................................35

Table 13 IPLLO Register ...........................................................................................................35

Table 14 IPLHI Register ............................................................................................................35

Table 15 Interrupt Vector Spacing .............................................................................................36

Table 16 Boot Time Mode Stream .............................................................................................37

Table 17 System Interface .........................................................................................................38

Table 18 Clock/Control Interface ...............................................................................................39

Table 19 Interrupt Interface .......................................................................................................40

Table 20 JTAG Interface ...........................................................................................................40

Table 21 Initialization Interface ..................................................................................................40

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