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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 39/52頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
39
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
Table 18
Clock/Control Interface
Pin Name
SysADC(7:0)
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data
cycles.
SysCmd(8:0)
Input/Output
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
SysCmdP
Input/Output
System Command/Data Identifier Bus Parity
For the RM7065A, unused on input and zero on output.
Type
Description
SysClock
Input
System clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization
VccP
Input
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to
VccInt through a filter circuit.
VssP
Input
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to
VssInt through a filter circuit.
Pin Name
Type
Description
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