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| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 37/52頁 |
| 文件大小： | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
37
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
Table 16 Boot Time Mode Stream
Mode bit
Description
Mode bit
Description
0
Reserved: must be zero
17:16
System configuration identifiers - software
visible in processor Config[21..20] register
4:1
Write-back data rate
0:
1:
2:
3:
4:
5:
6:
7:
8:
9-15: reserved
DDDD
DDxDDx
DDxxDDxx
DxDxDxDx
DDxxxDDxxx
DDxxxxDDxxxx
DxxDxxDxxDxx
DDxxxxxxDDxxxxxx
DxxxDxxxDxxxDxxx
19:18
Reserved: Must be zero
7:5
SysClock to Pclock Multiplier
Mode bit 20 = 0 / Mode bit 20 = 1
0:
1:
2:
3:
4:
5:
6:
7:
Multiply by 2/x
Multiply by 3/x
Multiply by 4/x
Multiply by 5/2.5
Multiply by 6/x
Multiply by 7/3.5
Multiply by 8/x
Multiply by 9/4.5
20
Pclock to SysClock multipliers.
0:
1:
Integer multipliers (2,3,4,5,6,7,8,9)
Half integer multipliers (2.5,3.5,4.5)
8
Specifies byte ordering. Logically ORed
with BigEndian input signal.
0:
1:
Little endian
Big endian
23:21
Reserved: Must be zero
10:9
Non-Block Write Control
00:
01:
10:
11:
R4000 compatible non-block writes
reserved
pipelined non-block writes
non-block write re-issue
24
JTLB Size.
0: 48 dual-entry
1: 64 dual-entry
11
Timer Interrupt Enable/Disable
0:
1:
External
Int[5]*
gated to
IP[7]
Internal Timer Interrupt gated to
IP[7]
25
On-chip secondary cache control.
0:
1:
Disable
Enable
12
Reserved: Must be zero
26
Enable two outstanding reads with out-of-
order return
0:
1:
Disable
Enable
14:13
Output driver strength - 100% = fastest
00:
01:
10:
11:
67% strength
50% strength
100% strength
83% strength
255:27
Reserved: Must be zero
15
Reserved: Must be zero
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