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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
27
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
integral clock multipliers, thereby providing greater granularity when selecting pipeline and
system interface frequencies.
The
SysAD
interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit command
bus. In addition, there are ten handshake signals and ten interrupt inputs. The interface is capable
of transferring data between the processor and memory at a peak rate of 1000 MB/sec with a 125
MHz SysClock.
Figure 7 shows a typical embedded system using the RM7065A. This example shows a system
with a bank of DRAMs and an interface ASIC which provides DRAM control as well as an I/O
port.
Figure 7 Typical Embedded System Block Diagram
4.25 System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM7065A and the rest of the system. It is protected with an 8-bit parity check bus,
SysADC[7:0]
.
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The data rate and the bus frequency at which the RM7065A transmits data to
the system interface are programmable at boot time via mode control bits. In addition, the rate at
which the processor receives data is fully controlled by the external device. Therefore, either a low
cost interface requiring no read or write buffering, or a faster, high-performance interface can be
designed to communicate with the RM7065A.
4.26 System Command Bus
The RM7065A interface has a 9-bit System Command bus,
SysCmd[8:0]
. The command bus
indicates whether the
SysAD
bus carries address or data information on a per-clock basis. If the
SysAD
bus carries address, the
SysCmd
bus indicates the transaction type (for example, a read or
write). If the
SysAD
bus carries data, then the
SysCmd
bus contains information about the data
(for example, this is the last data word transmitted, or the data contains an error). The
SysCmd
bus
is bidirectional to support both processor requests and external requests to the RM7065A.
Processor requests are initiated by the RM7065A and responded to by an external device. External
requests are issued by an external device and require the RM7065A to respond.
The RM7065A supports one- to eight-byte transfers as well as 32-byte block transfers on the
SysAD
bus. In the case of a sub-doubleword transfer, the 3 low-order address bits give the byte
address of the transfer, and the
SysCmd
bus indicates the number of bytes being transferred.
RM7065A
Memory I/O
Controller
DRAM
Flash/
Boot
ROM
Control
Address
x
x
72
PCI Bus
72
25
Latch
72
8
SysAD Bus
SysCmd
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