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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
26
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
Table 7 Cache Locking Control
Lock
Enable
4.22 Cache Management
To improve the performance of critical data movement operations in the embedded environment,
the RM7065A significantly improves the speed of operation of certain critical cache management
operations. In particular, the speed of the Hit-Writeback-Invalidate and Hit-Invalidate cache
operations has been improved, in some cases by an order of magnitude, over that of other MIPS
processors. For example, Table 8 compares the RM7065A with the R4000 processor.
Table 8 Penalty Cycles
For the Hit-Dirty case of Hit-Writeback-Invalidate in Table 8 above, if the writeback buffer is full
from some previous cache eviction, then n is the number of cycles required to empty the writeback
buffer. If the buffer is empty then n is zero.
The penalty value in Table 8 is the number of processor cycles beyond the one cycle required to
issue the instruction that is required to implement the operation.
4.23 Primary Write Buffer
Writes to secondary cache or external memory, whether cache miss write-backs or stores to
uncached or write-through addresses, use the integrated primary write buffer. The write buffer
holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-back
and allows the processor to proceed in parallel with memory update. For uncached and write-
through stores, the write buffer significantly increases performance by decoupling the
SysAD
bus
transfers from the instruction execution stream.
4.24 System Interface
The RM7065A provides a high-performance 64-bit system interface which is compatible with the
RM5200 Family. As an enhancement to the
SysAD
bus interface, the RM7065A allows half-
Cache
Set Select
Activate
Primary I
ECC[27]
ECC[28]=0
ECC[28]=1
A
B
Fill_I
Primary D
ECC[26]
ECC[28]=0
ECC[28]=1
A
B
Load/Store
Secondary
ECC[25]
ECC[28]=0
ECC[28]=1
A
B
Fill_I or
Load/Store
Operation
Condition
Penalty
RM7065A
R4000
Hit-Writeback-
Invalidate
Miss
0
7
Hit-Clean
3
12
Hit-Dirty
3+n
14+n
Hit-Invalidate
Miss
0
7
Hit
2
9
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