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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 38/52頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
38
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
5
Pin Descriptions
The following is a list of control, data, clock, interrupt, and miscellaneous pins of the RM7065A.
Table 17
System Interface
Pin Name
Type
Description
ExtRqst*
Input
External request
Signals that the system interface is submitting an external request.
Release*
Output
Release interface
Signals that the processor is releasing the system interface to slave
state
RdRdy*
Input
Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready
Signals that an external agent can now accept a processor write
request.
ValidIn*
Input
Valid Input
Signals that an external agent is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd bus.
PRqst*
Output
Processor Request
When asserted this signal requests that control of the system interface
be returned to the processor. This is enabled by Mode Bit 26.
PAck*
Input
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the
processor that it has been granted control of the system interface.
RspSwap*
Input
Response Swap
RspSwap* is used by the external agent to signal the processor when it
is about to return a memory reference out of order; i.e., of two
outstanding memory references, the data for the second reference is
being returned ahead of the data for the first reference. Note that this
signal works as a toggle; i.e., for each cycle that it is held asserted the
order of return is reversed. By default, anytime the processor issues a
second read it is assumed that the reads will be returned in order; i.e.,
no action is required if the reads are indeed returned in order. This is
enabled by Mode Bit 26.
RdType
Output
Read Type
During the address cycle of a read request, RdType indicates whether
the read request is an instruction read or a data read.
SysAD(63:0)
Input/Output
System address/data bus
A 64-bit address and data bus for communication between the
processor and an external agent.
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