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參數(shù)資料
| 型號： | RM7065A-400T |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 24/52頁 |
| 文件大小： | 901K |
| 代理商： | RM7065A-400T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use
Document ID: PMC-2010145, Issue 3
24
RM7065A Microprocessor with On-Chip Secondary Cache Data Sheet
Released
execute a store every processor cycle and to perform back-to-back stores without penalty. In the
event of a store immediately followed by a load to the same address, a combined merge and cache
write occurs such that no penalty is incurred.
4.19 Secondary Cache
The RM7065A has an integrated 256 KB, four-way set associative, block write-back secondary
cache. The secondary cache has a 32-byte line size, a 64-bit bus width to match the system
interface and primary cache bus widths, and is protected with doubleword parity. The secondary
cache tag array holds a 20-bit physical address, 2 control bits, a three bit cache state field, and two
parity bits.
By integrating a secondary cache, the RM7065A is able to decrease the latency of a primary cache
miss without significantly increasing the number of pins and the amount of power required by the
processor. From a technology point of view, integrating a secondary cache leverages CMOS
technology by using silicon to build the structures that are most amenable to silicon technology;
building very dense, low power memory arrays rather than large power hungry I/O buffers.
Further benefits of an integrated secondary cache are flexibility in the cache organization and
management policies that are not practical with an external cache. Two previously mentioned
examples are the 4-way associativity and write-back cache protocol.
A third management policy for which integration affords flexibility is cache hierarchy
management. With multiple levels of cache, it is necessary to specify a policy for dealing with
cases where two cache lines at level n of the hierarchy could possibly be sharing an entry in level
n+1 of the hierarchy.
The RM7065A allows entries to be stored in the primary caches that do not necessarily have a
corresponding entry in the secondary; the RM7065A does not force the primaries to be a subset of
the secondary. For example, if primary cache line A is being filled and a cache line already exists
in the secondary for primary cache line B at the location where primary A’s line would reside, then
that secondary entry is replaced by an entry corresponding to primary cache line A and no action
occurs in the primary for cache line B. This operation creates the aforementioned scenario where
the primary cache line, which initially had a corresponding secondary entry, no longer has such an
entry. Such a primary line is called an
orphan
. In general, cache lines at level n+1 of the hierarchy
are called
parents
of level n’s
children
.
Another RM7065A cache management optimization occurs for the case of a secondary cache line
replacement where the secondary line is dirty and has a corresponding dirty line in the primary. In
this case, since it is permissible to leave the dirty line in the primary, it is not necessary to write the
secondary line back to main memory. Taking this scenario one step further, a final optimization
occurs when the aforementioned dirty primary line is replaced by another line and must be written
back. In this case it is written directly to memory, bypassing the secondary cache.
4.20 Secondary Caching Protocols
Unlike the primary data cache, the secondary cache supports only uncached and block write-back.
As noted earlier, cache lines managed with either of the write-through protocols are not placed in
the secondary cache. A new caching attribute,
write-back with secondary bypass
, allows the
secondary cache to be bypassed entirely. When this attribute is selected, the secondary cache is not
filled on load misses and are not written on dirty write-backs from the primary cache
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