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參數(shù)資料
| 型號： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 113/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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S1C63808 TECHNICAL MANUAL
EPSON
49
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
4.8 Stopwatch Timer
4.8.1 Configuration of stopwatch timer
The S1C63808 has a 1/1,000 sec stopwatch timer. The stopwatch timer is configured of a 3-stage, 4-bit
BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read
out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software.
In addition it has a direct input function that controls the stopwatch timer RUN/STOP and LAP using the
input ports K00 and K01.
Figure 4.8.1.1 is the block diagram of the stopwatch timer.
Data bus
1 Hz interrupt request
1,000 / 1,024
prescaler
fOSC1/32
(1,024 Hz)
1/1,000 sec
counter
1/100 sec
counter
1/10 sec
counter
Capture buffer
SWD0–3
reading
SWD4–7
reading
SWD8–11
reading
[SWRST]
10 Hz interrupt request
Capture
control
circuit
[SWRUN]
[EDIR]
[CRNWF]
[DKM2–0]
[LCURF]
Direct RUN interrupt request
Direct LAP interrupt request
(1,000 Hz)
Direct
input
control
[SWDIR]
K01
K00
K02–K13
Fig. 4.8.1.1 Block diagram of stopwatch timer
The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch
stopwatch functions can be realized easily with software.
4.8.2 Counter and prescaler
The stopwatch timer is configured of four-bit BCD counters SWD0–3, SWD4–7 and SWD8–11.
The counter SWD0–3, at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the
prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter
SWD4–7 has a 100 Hz signal generated by the counter SWD0–3 for the input clock. It count-up every
1/100 sec, and generated 10 Hz signal. The counter SWD8–11 has an approximated 10 Hz signal gener-
ated by the counter SWD4–7 for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal.
The prescaler inputs a 1,024 Hz clock dividing fOSC1 (output from the OSC1 oscillation circuit), and
outputs 1,000 Hz counting clock for SWD0–3. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from
1,024 pulses that are input to the prescaler every second are taken out.
When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately
after to the prescaler will be pulled out.
<Counter value (msec) in which the pulse correction is performed>
39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979
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