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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 39/159頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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S1C63808 TECHNICAL MANUAL
EPSON
125
CHAPTER 5: SUMMARY OF NOTES
(3)Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned on and off by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.
(5) For the reason below, pay attention to the reload data write timing when changing the interval of the
programmable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as in
the figure).
Input clock
Counter data
(continuous mode)
(Reload data = 25H)
03H
02H
01H
00H
25H
24H
Counter data is determined by reloading.
Underflow (interrupt is generated)
Fig. 5.2.2 Reload timing for programmable timer
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period . Be especially careful when using the OSC1 (low-
speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3
(high-speed clock).
Serial interface
(1) Be sure to initialize the serial interface mode in the transmit/receive disabled status (TXENx = RXENx
= "0").
(2) Do not perform double trigger (writing "1") to TXTRGx (RXTRGx) when the serial interface is in the
transmitting (receiving) operation.
(3) In the clock synchronous mode, since one clock line (SCLKx) is shared for both transmitting and
receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Consequently, be sure not to write "1" to RXTRGx (TXTRGx) when TXTRGx (RXTRGx) is "1".
(4) When a parity error or framing error is generated during receiving in the asynchronous mode, the
receiving error interrupt factor flag ISERx is set to "1" prior to the receive completion interrupt factor
flag ISRCx for the time indicated in Table 5.2.1. Consequently, when an error is generated, you should
reset the receiving complete interrupt factor flag ISRCx to "0" by providing a wait time in error
processing routines and similar routines.
When an overrun error is generated, the receiving complete interrupt factor flag ISRCx is not set to "1"
and a receiving complete interrupt is not generated.
Table 5.2.1 Time difference between ISERx and ISRCx on error generation
Clock source
Time difference
fOSC3 / n
Programmable timer
1/2 cycles of fOSC3 / n
1 cycle of timer 1 underflow
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