參數資料
型號： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數： 150/159頁
文件大小： 1200K
代理商： S1C63158D0A010P
82
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.10.7 Operation of asynchronous transfer
Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the
back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully
synchronized clock on the transmit side and the receive side, but rather transmission is done while
adopting the synchronization at the start/stop bits that have attached before and after each piece of data.
The RS-232C interface functions can be easily realized by selecting this transfer mode.
This interface has separate transmit and receive shift registers and is designed to permit full duplex
transmission to be done simultaneously for transmitting and receiving.
For transfer data in the 7-bit asynchronous mode, either 7 bits data (no parity) or 7 bits data + parity bit
can be selected. In the 8-bit asynchronous mode, either 8 bits data (no parity) or 8 bits data + parity bit
can be selected.
Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting
data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the
program.
The start bit length is fixed at 1 bit. For the stop bit length, either 1 bit or 2 bits can be selected using the
stop bit select register STPBx. Whether data is transmitted/received from LSB (bit 0) or MSB (bit 7) it can
be switched using the data input/output permutation select register SDPx.
Sampling
clock
LSB first
8bit data
D0 D1 D2 D3 D4 D5 D6 D7
s1
s2
7bit data
+parity
D0 D1 D2 D3 D4 D5 D6
p
s1
s2
8bit data
+parity
D0 D1 D2 D3 D4 D5 D6 D7
s1
p
s2
7bit data
D0 D1 D2 D3 D4 D5 D6
s1
s2
Sampling
clock
MSB first
8bit data
D7 D6 D5 D4 D3 D2 D1 D0
s1
s2
7bit data
+parity
D6 D5 D4 D3 D2 D1 D0
p
s1
s2
8bit data
+parity
D7 D6 D5 D4 D3 D2 D1 D0
s1
p
s2
s1
s2
p
: Start bit (Low level, 1 bit)
: Stop bit (High level, 1 bit or 2 bits)
: Parity bit
7bit data
D6 D5 D4 D3 D2 D1 D0
s1
s2
Fig. 4.10.7.1 Transfer data configuration for asynchronous system
Here following, we will explain the control sequence and operation for initialization and transmitting /
receiving in case of asynchronous data transfer. See "4.10.8 Interrupt function" for the serial interface
interrupts.
Initialization of serial interface
The below initialization must be done in cases of asynchronous system transfer.
(1) Setting of transmitting/receiving disable
To set the serial interface into a status in which both transmitting and receiving are disabled, "0"
must be written to both the transmit enable register TXENx and the receive enable register RXENx.
Fix these two registers to a disable status until data transfer actually begins.
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