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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 141/159頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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74
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Clock synchronous master mode
In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and 8-
bit clock synchronous serial transfers can be performed with this serial interface as the master.
The synchronous clock is also output from the SCLKx terminal which enables control of the external
(slave side) serial I/O device. Since the SRDYx terminal is not utilized in this mode, it can be used as
an I/O port.
Figure 4.10.3.1(a) shows the connection example of input/output terminals in the clock synchronous
master mode.
Clock synchronous slave mode
In this mode, a synchronous clock from the external (master side) serial input/output device is
utilized and 8-bit clock synchronous serial transfers can be performed with this serial interface as the
slave. The synchronous clock is input to the SCLKx terminal and is utilized by this interface as the
synchronous clock. Furthermore, the SRDYx signal indicating the transmit-receive ready status is
output from the SRDYx terminal in accordance with the serial interface operating status.
In the slave mode, the settings for registers SCSx0 and SCSx1 used to select the clock source are
invalid. Figure 4.10.3.1(b) shows the connection example of input/output terminals in the clock
synchronous slave mode.
7-bit asynchronous mode
In this mode, 7-bit asynchronous transfer can be performed. Parity check during data reception and
addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 7
bits with or without parity. Since this mode employs the internal clock, the SCLKx terminal is not
used. Furthermore, since the SRDYx terminal is not utilized either, both of these terminals can be used
as I/O ports. Figure 4.10.3.1(c) shows the connection example of input/output terminals in the
asynchronous mode.
8-bit asynchronous mode
In this mode, 8-bit asynchronous transfer can be performed. Parity check during data reception and
addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 8
bits with or without parity. Since this mode employs the internal clock, the SCLKx terminal is not
used. Furthermore, since the SRDYx terminal is not utilized either, both of these terminals can be used
as I/O ports. Figure 4.10.3.1(c) shows the connection example of input/output terminals in the
asynchronous mode.
Data input
Data output
CLOCK output
READY input
SINx(P10/P20)
SOUTx(P11/P21)
SCLKx(P12/P22)
Input port
External
serial device
S1C63808
Data input
Data output
CLOCK output
READY input
SINx(P10/P20)
SOUTx(P11/P21)
SCLKx(P12/P22)
SRDYx(P13/P23)
External
serial device
S1C63808
(a) Clock synchronous master mode
(b) Clock synchronous slave mode
Data input
Data output
SINx(P10/P20)
SOUTx(P11/P21)
External
serial device
S1C63808
(c) Asynchronous 7-bit/8-bit mode
Fig. 4.10.3.1 Connection examples of serial interface I/O terminals
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