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參數(shù)資料
| 型號(hào)： | S1C63158D0A010P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 38/159頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | S1C63158D0A010P |
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124
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
Output port
(1) When using the output port (R01, R02, R03) as the special output port (BZ, TOUT, FOUT), fix the data
register (R01, R02, R03) at "1" and the high impedance control register (R01HIZ, R02HIZ, R03HIZ) at
"0" (data output).
Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R01, R02 and R03 registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register (R01HIZ, R02HIZ, R03HIZ).
(2) A hazard may occur when the BZ signal, FOUT signal and the TOUT signal are turned on and off.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
I/O port
When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of the
waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 375 k
(Max.)
Clock timer
Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
Stopwatch timer
(1) The interrupt factor flag should be reset after resetting the stopwatch timer.
(2) Be sure to data reading in the order of SWD0–3
→ SWD4–7 → SWD8–11.
(3) When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after
reading the SWD8–11 and check whether the data has been renewed or not.
(4) When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read the
LAP data carry-up request flag LCURF before processing and check whether carry-up is needed or not.
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. Furthermore,
the high-order 4 bits (PTDx4–PTDx7) should be read within 0.73 msec (when fOSC1 is 32.768 kHz) of
reading the low-order 4 bits (PTDx0–PTDx3).
The counter data in 16-bit mode must be read in the order below.
PTD00–PTD03
→ PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the
PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1).
The PTRUNx register maintains "1" for reading until the timer actually stops.
Figure 5.2.1 shows the timing chart for the RUN/STOP control.
PTRUNx (WR)
PTDx0–PTDx7
42H
41H 40H 3FH 3EH
3DH
PTRUNx (RD)
Input clock
"1" (RUN)
writing
"0" (STOP)
writing
Fig. 5.2.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
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