參數(shù)資料
型號： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 6/159頁
文件大?。?/td> 1200K
代理商： S1C63158D0A010P
S1C63808 TECHNICAL MANUAL
EPSON
95
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
PER1: Serial interface 1 parity error flag (FF67HD1)
PER2: Serial interface 2 parity error flag (FF17HD1)
Indicates the generation of a parity error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
PERx is an error flag that indicates the generation of a parity error and becomes "1" when an error has
been generated.
When a parity check is performed in the asynchronous mode, a parity error will be generated if data that
does not match the parity is received.
PERx is reset to "0" by writing "1".
PERx is set to "0" at initial reset or when RXENx is set to "0".
FER1: Serial interface 1 framing error flag (FF67HD2)
FER2: Serial interface 2 framing error flag (FF17HD2)
Indicates the generation of a framing error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
FERx is an error flag that indicates the generation of a framing error and becomes "1" when an error has
been generated.
When the stop bit for the receiving in the asynchronous mode has become "0", a framing error is gener-
ated.
FERx is reset to "0" by writing "1".
FERx is set to "0" at initial reset or when RXENx is set to "0".
EISRC1, EISTR1, EISER1: Serial interface 1 interrupt mask registers (FFE1HD0, D1, D2)
EISRC2, EISTR2, EISER2: Serial interface 2 interrupt mask registers (FFE0HD0, D1, D2)
Enables or disables the generation of an interrupt for the CPU.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
EISRCx, EISTRx and EISERx are interrupt mask registers that respectively correspond to the interrupt
factors for receive completion, transmit completion and receive error. Interrupts set to "1" are enabled and
interrupts set to "0" are disabled.
At initial reset, these registers are set to "0".
ISRC1, ISTR1, ISER1: Serial interface 1 interrupt factor flags (FFF1HD0, D1, D2)
ISRC2, ISTR2, ISER2: Serial interface 2 interrupt factor flags (FFF0HD0, D1, D2)
Indicates the serial interface interrupt generation status.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
ISRCx, ISTRx and ISERx are interrupt factor flags that respectively correspond to the interrupts for receive
completion, transmit completion and receive error, and are set to "1" by generation of each factor.
Transmit completion interrupt factor is generated at the point where the data transmission of the shift
register has been completed.
Receive completion interrupt factor is generated at the point where the received data has been transferred
into the receive data buffer.
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