參數(shù)資料
型號： S1C63158D0A010P
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 3/159頁
文件大小： 1200K
代理商： S1C63158D0A010P
92
EPSON
S1C63808 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SDP1: Serial interface 1 data input/output permutation select register (FF6AHD0)
SDP2: Serial interface 2 data input/output permutation select register (FF1AHD0)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
STPB1: Serial interface 1 stop bit select register (FF6AHD1)
STPB2: Serial interface 2 stop bit select register (FF1AHD1)
Selects the stop bit length for asynchronous data transfer.
When "1" is written: 2 bits
When "0" is written: 1 bit
Reading: Valid
STPBx is the stop bit select register that is effective in asynchronous mode. When "1" is written to STPBx,
the stop bit length is set to 2 bits, and when "0" is written, it is set to 1 bit.
In clock synchronous mode, no start/stop bits can be added to transfer data. Therefore, STPBx is ineffec-
tive.
At initial reset, STPBx is set to "0" (1 bit).
EPR1: Serial interface 1 parity enable register (FF65HD3)
EPR2: Serial interface 2 parity enable register (FF15HD3)
Selects the parity function.
When "1" is written: With parity
When "0" is written: Non parity
Reading: Valid
Selects whether or not to check parity of the received data and to add a parity bit to the transmitting data.
When "1" is written to EPRx, the most significant bit of the received data is considered to be the parity bit
and a parity check is executed. A parity bit is added to the transmitting data. When "0" is written, neither
checking is done nor is a parity bit added.
Parity is valid only in asynchronous mode and the EPRx setting becomes invalid in the clock synchro-
nous mode.
At initial reset, this register is set to "0".
PMD1: Serial interface 1 parity mode selection register (FF65HD2)
PMD2: Serial interface 2 parity mode selection register (FF15HD2)
Selects odd parity/even parity.
When "1" is written: Odd parity
When "0" is written: Even parity
Reading: Valid
When "1" is written to PMDx, odd parity is selected and even parity is selected when "0" is written. The
parity check and addition of a parity bit is only valid when "1" has been written to EPRx. When "0" has
been written to EPRx, the parity setting by PMDx becomes invalid.
At initial reset, this register is set to "0".
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