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20
Revision 1.1
G
Signal Definitions
(Continued)
C8
2
MD53
I/O
IN
T
,
TS
2/5
V
IO
---
C9
2
MD55
I/O
IN
T
,
TS
2/5
V
IO
---
C10
MA7
O
O
2/5
V
IO
---
C11
BA0
O
O
2/5
V
IO
---
C12
BA1
O
O
2/5
V
IO
---
C13
MA11
O
O
2/5
V
IO
---
C14
DQM6
O
O
2/5
V
IO
---
C15
DQM7
O
O
2/5
V
IO
---
C16
2
MD56
I/O
IN
T
,
TS
2/5
V
IO
---
C17
2
MD58
I/O
IN
T
,
TS
2/5
V
IO
---
C18
2
MD60
I/O
IN
T
,
TS
2/5
V
IO
---
C19
2
MD62
I/O
IN
T
,
TS
2/5
V
IO
---
C20
GXCLK
O
O
2/5
V
IO
PMR[29] = 0 and
PMR[6] = 1
IRTX
O
O
2/5
PMR[29] = 0 and
PMR[6] = 0
TEST3
O
O
2/5
PMR[29] = 1 and
PMR[6] = 1
C21
WR#
O
O
3/5
V
IO
---
C22
IOW#
O
O
3/5
V
IO
PMR[21] = x and
PMR[2] = 0
DOCW#
O
(PU
22.5
)
O
3/5
PMR[21] = 1 and
PMR[2] = 1
GPIO15
I/O
(PU
22.5
)
IN
TS
,
O
8/8
PMR[21] = 0 and
PMR[2] = 1
C23
ROMCS#
O
O
3/5
V
IO
---
BOOT16
I
(PD
100
)
IN
TS
V
IO
Strap
C24
V
IO
PWR
---
---
---
C25
GPIO35
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14] = 0
LAD3
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14] = 1
C26
GPIO36
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14] = 0
LDRQ#
I
(PU
22.5
)
IN
PCI
PMR[14] = 1
D1
SDTEST1
O
O
2/5
V
IO
---
D2
MA12
O
O
2/5
V
IO
---
D3
CASA#
O
O
2/5
V
IO
---
D4
SDCLK_IN
I
IN
T
V
IO
---
D5
SDTEST3
O
O
2/5
V
IO
---
D6
2
MD48
I/O
IN
T
,
TS
2/5
V
IO
---
D7
2
MD50
I/O
IN
T
,
TS
2/5
V
IO
---
D8
V
IO
PWR
---
---
---
D9
V
SS
GND
---
---
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
D10
V
IO
PWR
---
---
---
D11
V
SS
GND
---
---
---
D12
V
CORE
PWR
---
---
---
D13
V
SS
GND
---
---
---
D14
V
SS
GND
---
---
---
D15
V
CORE
PWR
---
---
---
D16
V
SS
GND
---
---
---
D17
V
IO
PWR
---
---
---
D18
V
SS
GND
---
---
---
D19
V
IO
PWR
---
---
---
D20
NC
---
---
---
---
D21
GPIO20
I/O
(PU
22.5
)
IN
TS
,
O
8/8
V
IO
PMR[7] = 0
DOCCS#
O
O
3/5
PMR[7] = 1
D22
GPIO14
I/O
PU
22.5)
IN
TS
,
O
8/8
V
IO
PMR[21] = 0 and
PMR[2] = 0
IOCS1#
O
(PU
22.5
)
O
3/5
PMR[21] = 0 and
PMR[2] = 1
IOR#
O
O
3/5
PMR[21] = 1 and
PMR[2] = 0
DOCR#
O
O
3/5
PMR[21] = 1 and
PMR[2] = 1
D23
RD#
O
O
3/5
V
IO
---
CLKSEL0
I
(PD
100
)
IN
TS
Strap
D24
AD7
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A7
O
O
PCI
D25
GPIO33
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14] = 0
LAD1
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14] = 1
D26
GPIO34
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14] = 0
LAD2
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14] = 1
E1
2
MD14
I/O
IN
T
,
TS
2/5
V
IO
---
E2
2
MD15
I/O
IN
T
,
TS
2/5
V
IO
---
E3
SDTEST4
O
O
2/5
V
IO
---
E4
SDCLK0
O
O
2/5
V
IO
---
E23
AD8
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A8
O
O
PCI
E24
C/BE0#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D8
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
E25
AD0
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A0
O
O
PCI
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
Table 2-2. Ball Assignment - Sorted by Ball Number (Continued)