Revision 1.1
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G
Electrical Specifications
(Continued)
7.1.3
Table 7-2 lists the power supplies of the SC1100 and provides the device operating conditions.
Operating Conditions
Note:
1)
All power sources must be connected to the SC1100,
even if the function is not used.
2)
Voltages must be applied according to the sequence
set forth in Section 7.3.12 on page 339.
3)
V
SBL
and V
CORE
must adhere at all times to the follow-
ing requirement: V
SBL
> V
CORE
.
4)
The power planes of the SC1100 can be turned on or
off. For more information, see Section 5.2.9 "Power
Management Logic" on page 134.
5)
It is recommended that the voltage difference between
V
CORE
and V
SBL
be less than 0.25V in order to reduce
leakage current. If the voltage difference exceeds
0.25V, excessive leakage current is used in gates that
are connected on the boundary between voltage
domains.
6)
It is recommended that the voltage difference between
V
IO
and V
SB
be less than 0.25V in order to reduce
leakage current. If the voltage difference exceeds
0.25V, excessive leakage current is used in gates that
are connected on the boundary between voltage
domains.
7)
V
SB
, V
SBL
and V
BAT
must be on if any other voltage is
applied. V
SB
and V
BAT
voltages can be applied sepa-
rately. See Section 7.3.12 "Power-Up Sequencing" on
page 339.
Table 7-2. Operating Conditions
Symbol
1
1.
For V
IH
(Input High Voltage), V
IL
(Input Low Voltage), I
OH
(Output High Current), and I
OL
(Output Low Current) operating
conditions refer to Section 7.2 "DC Characteristics" on page 286.
Parameter
Min
Typ
Max
Unit
Comments
T
C
Operating case temperature.
0
-
85
o
C
AV
CCUSB
Analog power supply. Powers internal ana-
log circuits and some external signals (see
Table 7-3).
3.135
3.3
3.465
V
V
BAT
Battery supply voltage. Powers RTC and
ACPI when V
BAT
is greater than V
SB
(by at
least 0.5V), and some external signals (see
Table 7-3).
2.4
3.0
3.6
V
V
IO
I/O buffer power supply. Powers most of
the external signals (see Table 7-3); certain
signals within this power plane are 5V
tolerant.
3.135
3.3
3.465
V
V
CORE
Core processor and internal digital power supply. Powers internal digital logic, including internal frequency
multipliers.
233 MHz Core clock frequency.
1.71
1.8
1.89
V
266 MHz Core clock frequency.
1.9
2.0
2.1
V
300 MHz Core clock frequency.
TBD
TBD
TBD
V
V
PLL
PLL. Internal Phase Locked Loop (PLL)
power supply.
3.135
3.3
3.465
V
V
SB
Standby power supply. Powers RTC and
ACPI when V
SB
is greater than V
BAT
-0.5V,
and some external signals (see Table 7-3).
3.135
3.3
3.465
V
V
SBL
Standby logic. Powers internal logic needed to support Standby V
SB
.
V
SBL
(ball AD16) requires a 0.1 μF bypass capacitor to V
SS
.
233 MHz Core clock frequency.
1.71
1.8
1.89
V
266 MHz Core clock frequency.
1.9
2.0
2.1
V
300 MHz Core clock frequency.
TBD
TBD
TBD
V