Revision 1.1
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G
General Configuration Block
(Continued)
Offset 34h
Width: DWORD
Power-on reset value: The BOOT16 strap pin selects "Enable 16-Bit Wide Boot Memory".
Miscellaneous Configuration Register - MCR (R/W)
Reset Value: 0000001h
31
30
Reserved.
Always write 0.
FPCI_MON (Ball AB25) Strap Status. (Read Only)
Represents the value of the strap that is latched after power-on reset.
Indicates if Fast-PCI monitoring output signals are enabled via strapping option.
0: Disable (FPCI_MON = 0).
1: Enable (FPCI_MON = 1).
In addition to the strapping option, Fast-PCI monitoring output signals can also be enabled via PMR[27]. See PMR[27] bit
description for a list of signals that are enabled when either option is used.
Reserved.
Always write 0.
F5B5_16 (Enable 16-Bit Wide F5BAR5CS# Access).
Enables the 16-line access to F5BAR5CS# in the Sub-ISA interface.
0: 8-bit wide F5BAR5CS# access is used.
1: 16-bit wide F5BAR5CS# access is used.
IBUS16 (Invert BUS16).
This bit inverts the meaning of MCR[3] (bit 3 of this register).
0
:
BUS16 is as described for MCR[3].
1: BUS16 meaning is inverted: if MCR[3] = 0, ROMCS# access is 16 bits wide; if MCR[3] = 1, ROMCS# access is 8 bits
wide.
F5B4ZWS (Enable ZWS for F5BAR4CS# Access).
Enables internal activation of ZWS# (Zero Wait States) control for
F5BAR4CS# access.
0: ZWS is not active for F5BAR4CS# access.
1: ZWS is active for F5BAR4CS# access.
IO1ZWS (Enable ZWS# for IOCS1# Access).
Enables internal activation of ZWS# (Zero Wait States) control for IOCS1#
access.
0: ZWS# is not active for IOCS1# access.
1: ZWS# is active for IOCS1# access.
IO0ZWS (Enable ZWS# for IOCS0# Access).
Enables internal activation of ZWS# (Zero Wait States) control for IOCS0#
access.
0: ZWS# is not active for IOCS0# access.
1: ZWS# is active for IOCS0# access.
DOCZWS (Enable ZWS# for DOCCS# Access).
Enables internal activation of ZWS# (Zero Wait States) control for
DOCCS# access.
0: ZWS# is not active for DOCCS# access.
1: ZWS# is active for DOCCS# access.
ROMZWS (Enable ZWS# for ROMCS# Access).
Enables internal activation of ZWS# (Zero Wait States) control for
ROMCS# access.
0: ZWS# is not active for ROMCS# access.
1: ZWS# is active for ROMCS# access.
IO1_16 (Enable 16-Bit Wide IOCS1# Access).
Enables the16-line access to IOCS1# in the Sub-ISA interface.
0: 8-bit wide IOCS1# access is used.
1: 16-bit wide IOCS1# access is used.
IO0_16 (Enable 16-Bit Wide IOCS0# Access).
Enables the 16-line access to IOCS0# in the Sub-ISA interface.
0: 8-bit wide IOCS0# access is used.
1: 16-bit wide IOCS0# access is used.
DOC16 (Enable 16-Bit Wide DOCCS# Access).
Enables the 16-line access to DOCCS# in the Sub-ISA interface.
0: 8-bit wide DOCCS# access is used.
1: 16-bit wide DOCCS# access is used.
F5B4_16 (Enable 16-Bit Wide F5BAR4CS# Access).
Enables the 16-line access to F5BAR4CS# in the Sub-ISA interface.
0: 8-bit wide F5BAR4CS# access is used.
1: 16-bit wide F5BAR4CS# access is used.
29:16
15
14
13
12
11
10
9
8
7
6
5
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description