(VDD
參數(shù)資料
型號: SI3225PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 20/112頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
設計資源: Si3225PPTX-EVB Schematics/Layout
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3225
已供物品: 板,CD
Si3220/25 Si3200/02
Rev. 1.3
15
Not
Recommended
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Table 8. Si3200/2 Characteristics
(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TIP/RING Pulldown Transistor Satura-
tion Voltage
VOV
VRING – VBAT (Forward)
VTIP – VBAT (Reverse)
ILIM =22mA, IABIAS =4mA
ILIM =45mA,
IABIAS =16mA
3
V
TIP/RING Pullup Transistor
Saturation Voltage
VCM
GND – VTIP (Forward)
GND – VRING (Reverse)
ILIM =22mA
ILIM =45mA
3
V
Battery Switch Saturation
Impedance
RSAT
(VBAT – VBATH)/IOUT (Note 2)
15
OPEN State TIP/RING Leakage Current
ILKG
RL =0
100
A
Internal Blocking Diode Forward Voltage
VF
VBAT – VBATL (Note 2)
0.8
V
Notes:
1. VAC = 2.5 VPK, RLOAD = 600 .
2. IOUT =60mA.
Table 9. DC Characteristics (VDD, VDD1–VDD4 = 5V)
(VDD, VDD1 – VDD4 = 4.75 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input
Voltage
VIH
0.7 x VDD
—5.25
V
Low Level Input
Voltage
VIL
0.3 x VDD
V
High Level Output
Voltage
VOH
IO =8mA
VDD – 0.6
V
Low Level Output
Voltage
VOL
DTX, SDO, INT, SDITHRU:
IO =–8mA
——
0.4
V
BATSELa/b, RRDa/b,
GPOa/b, TRD1a/b,TRD2a/b:
IO =–40 mA
0.72
V
SDITHRU Internal
Pullup Resistance
20
30
k
Relay Driver Source
Impedance
ROUT
VDD1–VDD4 =4.75V
IO < 28 mA
—63
Relay Driver Sink
Impedance
RIN
VDD1–VDD4 =4.75V
IO < 85 mA
—11
Input Leakage Current
IL
——
±10
A
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