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| 型號： | SI3225PPTX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 85/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL W/DISCRETE INTERFACE |
| 設(shè)計資源： | Si3225PPTX-EVB Schematics/Layout |
| 標準包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3225 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
74
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
The control byte has the following structure and is presented on the SDI pin MSB first:
See Table 42 for bit definitions.
7
6
5
4
3210
BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3]
Table 42. SPI Control Interface
7
BRDCST
Indicates a broadcast operation that is intended for all devices in the daisy chain. This is
only valid for write operations since it would cause contention on the SDO pin during a
read.
6R/W
Read/Write Bit.
0 = Write operation.
1 = Read operation.
5
REG/RAM Register/RAM Access Bit.
0 = RAM access.
1 = Register access.
4
Reserved
3:0
CID[3:0]
Indicates the channel that is targeted by the operation. Note that the 4-bit channel value is
provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to
the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.)
As the CID information propagates down the daisy chain, each channel decrements the
CID by 1. The SDI nodes between devices reflect a decrement of 2 per device since each
device contains two channels. The device receiving a value of 0 in the CID field responds
to the SPI transaction. (See Figure 42.) If a broadcast to all devices connected to the chain
is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is pre-
sented to all channels regardless of the CID values.
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