參數(shù)資料
型號(hào): SI3225PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 26/112頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
設(shè)計(jì)資源: Si3225PPTX-EVB Schematics/Layout
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3225
已供物品: 板,CD
Si3220/25 Si3200/02
20
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
Table 14. Switching Characteristics—GCI Highway Serial Interface
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
Parameter1
Symbol
Test
Conditions
Min
Typ
Max
Units
PCLK Period (2.048 MHz PCLK Mode)
tp
—488
ns
PCLK Period (4.096 MHz PCLK Mode)
tp
—244
ns
FSYNC Period2
tfs
—125
s
PCLK Duty Cycle Tolerance
tdty
40
50
60
%
FSYNC Jitter Tolerance
tjitter
——
±120
ns
Rise Time, PCLK
tr
——
25
ns
Fall Time, PCLK
tf
——
25
ns
Delay Time, PCLK Rise to DTX Active
td1
——
20
ns
Delay Time, PCLK Rise to DTX Transition
td2
——
20
ns
Delay Time, PCLK Rise to DTX Tristate3
td3
——
20
ns
Setup Time, FSYNC Rise to PCLK Fall
tsu1
25
ns
Hold Time, PCLK Fall to FSYNC Fall
th1
20
ns
Setup Time, DRX Transition to PCLK Fall
tsu2
25
ns
Hold Time, PCLK Falling to DRX Transition
th2
20
ns
FSYNC Pulse Width
twfs
tp/2
ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and
fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
tsu1
t
h1
t
p
t
r
t
f
t
h2
t
d3
t
d2
t
d1
PCLK
FSYNC
DRX
DTX
t
fs
t
su2
Frame 0,
Bit 0
Frame 0,
Bit 0
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